Patents by Inventor Chih-Chin Yang

Chih-Chin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240160599
    Abstract: A serial communication bus system with a dynamic address table and its control method allows the master device to detect the removal of slave devices from the serial communication bus using allocated addresses and a common initial address through interactive polling. Additionally, when new slave devices connect to the bus, they can be directly detected, and non-conflicting new addresses can be assigned, eliminating the need to reassign addresses for all connected slave devices, as required in the conventional approach.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 16, 2024
    Inventors: Shun-Liang Yang, Chiun-Shiu Chen, Chih-Chin Yang
  • Publication number: 20240145919
    Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.
    Type: Application
    Filed: September 6, 2023
    Publication date: May 2, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Shih-Keng Huang, Chao-Hsu Wu, Chih-Wei Liao, Sheng-Chin Hsu, Hao-Hsiang Yang, Tse-Hsuan Wang
  • Publication number: 20240113429
    Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 4, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chia-Hung Chen, Chih-Wei Liao, Hau Yuen Tan, Hao-Hsiang Yang, Shih-Keng Huang
  • Publication number: 20240096838
    Abstract: A component-embedded packaging structure is provided, in which a plurality of metal layers are formed on an inactive surface of a semiconductor chip so as to serve as a buffer portion, and the semiconductor chip is disposed on a carrying portion with the buffer portion via an adhesive. Then, the semiconductor chip is encapsulated by an insulating layer, and a build-up circuit structure is formed on the insulating layer and electrically connected to the semiconductor chip. Therefore, the buffer portion can prevent delamination from occurring between the semiconductor chip and the adhesive on the carrying portion if the semiconductor chip has a CTE (Coefficient of Thermal Expansion) less than a CTE of the adhesive.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin HU, Shih-Ping HSU, Chih-Kuai YANG
  • Patent number: 11237900
    Abstract: A system for aggregating dataflow lineage information is disclosed. The system receives one or more input data elements and determines a dataflow path for the one or more input data elements. The dataflow path includes at least a data storage node and a computation node. Then, the system identifies a lineage control value associated with the data storage node and a version control value associated with the computation node. The system generates an output lineage for the one or more input data elements by appending the lineage control value to the version control value.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: February 1, 2022
    Assignee: Bank of America Corporation
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Patent number: 11146475
    Abstract: A system for performing an integrated data quality control is disclosed. The system determines a dataflow path for one or more input data elements. The, the system performs a lineage control check, a timeliness control check, and a variation control check on the dataflow path. If the dataflow path integrated scoring of the three controls is sufficient, the system determines that data related to the dataflow path is fit for use. If the dataflow path fails any one of the three checks, the system determines that data related to the dataflow path is not fit for use.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 12, 2021
    Assignee: Bank of America Corporation
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Patent number: 10812357
    Abstract: A system for performing a timeliness control is disclosed. The system identifies a dataflow path for performing timeliness control and identifies a first network node and a second network node of the dataflow path for determining a latency between the first and the second network node. The system determines an output lineage corresponding to the dataflow path and identifies, from the output lineage, a first control value associated with the first network node and a second control value associated with the second network node. Then, the system extracts a first timestamp from the first control value and a second timestamp from the second control value and determines the latency based on the first timestamp and the second timestamp. Although the intranode latency is described herein with respect to a first and second nodes, the intra-node latency can be determined for up to n nodes using the techniques described herein.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: October 20, 2020
    Assignee: Bank of America Corporation
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Patent number: 10803051
    Abstract: A system for validating a dataflow graph is disclosed. The system receives an input dataflow graph and compares the input dataflow graph to each of a plurality of pre-learned dataflow graphs. Each of the pre-learned dataflow graphs is associated with an occurrence rate. Then, the system identifies a pre-learned dataflow graph that matches the input dataflow graph and identifies an occurrence rate associated with the pre-learned dataflow graph. The system compares the occurrence rate with a pre-defined threshold for validating the input dataflow graph. If the occurrence rate exceeds the pre-defined threshold, the system determines that the input dataflow graph is a valid dataflow graph.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: October 13, 2020
    Assignee: Bank of America Corporation
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20200218600
    Abstract: A system for aggregating dataflow lineage information is disclosed. The system receives one or more input data elements and determines a dataflow path for the one or more input data elements. The dataflow path includes at least a data storage node and a computation node. Then, the system identifies a lineage control value associated with the data storage node and a version control value associated with the computation node. The system generates an output lineage for the one or more input data elements by appending the lineage control value to the version control value.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20200220799
    Abstract: A system for performing an integrated data quality control is disclosed. The system determines a dataflow path for one or more input data elements. The, the system performs a lineage control check, a timeliness control check, and a variation control check on the dataflow path. If the dataflow path integrated scoring of the three controls is sufficient, the system determines that data related to the dataflow path is fit for use. If the dataflow path fails any one of the three checks, the system determines that data related to the dataflow path is not fit for use.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20200117731
    Abstract: A system for validating a dataflow graph is disclosed. The system receives an input dataflow graph and compares the input dataflow graph to each of a plurality of pre-learned dataflow graphs. Each of the pre-learned dataflow graphs is associated with an occurrence rate. Then, the system identifies a pre-learned dataflow graph that matches the input dataflow graph and identifies an occurrence rate associated with the pre-learned dataflow graph. The system compares the occurrence rate with a pre-defined threshold for validating the input dataflow graph. If the occurrence rate exceeds the pre-defined threshold, the system determines that the input dataflow graph is a valid dataflow graph.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20200120028
    Abstract: A system for performing a variation control in a data network is disclosed. The system generates a distribution graph for a set of node values associated with a network node. The system determines a statistical confidence level for the distribution graph and determines a statistical confidence interval for the distribution graph based on the statistical confidence level. Then, the system receives a new node value associated with the network node and compares the new node value to the statistical confidence interval. If the new node value falls within the statistical confidence interval, the system determines that determining that the new node value is normal.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20200120008
    Abstract: A system for performing a timeliness control is disclosed. The system identifies a dataflow path for performing timeliness control and identifies a first network node and a second network node of the dataflow path for determining a latency between the first and the second network node. The system determines an output lineage corresponding to the dataflow path and identifies, from the output lineage, a first control value associated with the first network node and a second control value associated with the second network node. Then, the system extracts a first timestamp from the first control value and a second timestamp from the second control value and determines the latency based on the first timestamp and the second timestamp. Although the intranode latency is described herein with respect to a first and second nodes, the intra-node latency can be determined for up to n nodes using the techniques described herein.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20200120011
    Abstract: A system for performing an integrated data quality control is disclosed. The system determines a dataflow path for one or more input data elements. The, the system performs a lineage control check, a timeliness control check, and a variation control check on the dataflow path. If the dataflow path integrated scoring of the three controls is sufficient, the system determines that data related to the dataflow path is fit for use. If the dataflow path fails any one of the three checks, the system determines that data related to the dataflow path is not fit for use.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20200117535
    Abstract: A system for aggregating dataflow lineage information is disclosed. The system receives one or more input data elements and determines a dataflow path for the one or more input data elements. The dataflow path includes at least a data storage node and a computation node. Then, the system identifies a lineage control value associated with the data storage node and a version control value associated with the computation node. The system generates an output lineage for the one or more input data elements by appending the lineage control value to the version control value.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Patent number: 10623298
    Abstract: A system for performing an integrated data quality control is disclosed. The system determines a dataflow path for one or more input data elements. The, the system performs a lineage control check, a timeliness control check, and a variation control check on the dataflow path. If the dataflow path integrated scoring of the three controls is sufficient, the system determines that data related to the dataflow path is fit for use. If the dataflow path fails any one of the three checks, the system determines that data related to the dataflow path is not fit for use.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 14, 2020
    Assignee: Bank of America Corporation
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Patent number: 10621033
    Abstract: A system for aggregating dataflow lineage information is disclosed. The system receives one or more input data elements and determines a dataflow path for the one or more input data elements. The dataflow path includes at least a data storage node and a computation node. Then, the system identifies a lineage control value associated with the data storage node and a version control value associated with the computation node. The system generates an output lineage for the one or more input data elements by appending the lineage control value to the version control value.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 14, 2020
    Assignee: Bank of America Corporation
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Patent number: 10601712
    Abstract: A system for performing a variation control in a data network is disclosed. The system generates a distribution graph for a set of node values associated with a network node. The system determines a statistical confidence level for the distribution graph and determines a statistical confidence interval for the distribution graph based on the statistical confidence level. Then, the system receives a new node value associated with the network node and compares the new node value to the statistical confidence interval. If the new node value falls within the statistical confidence interval, the system determines that determining that the new node value is normal.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 24, 2020
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Amitava Deb, Sandip Gopal Bhatwadekar, Chih-Chin Yang, Jovan Cenev
  • Publication number: 20170207049
    Abstract: A system for actively detecting an alternating current (AC) load includes a first power interface, a second power interface, a switch unit, and a control unit. The first power interface is coupled to an AC source to receive and provide an AC voltage. The second power interface is configured to be coupled to an electronic equipment to provide the AC source to the electronic equipment and provide a connection signal according to whether the electronic equipment is coupled to the second power interface. The switch unit is coupled between the first power interface and the second power interface and receives a switch signal to determine whether the AC voltage is transmitted to the second power interface. The control unit is coupled to the second power interface and the switch unit to provide the switch signal according to the connection signal.
    Type: Application
    Filed: November 7, 2016
    Publication date: July 20, 2017
    Applicant: PROLIFIC TECHNOLOGY INC.
    Inventors: Chih-Chin Yang, Chia-Chang Hsu, Yun-Kuo Lee
  • Publication number: 20160154868
    Abstract: A data synchronizing system includes a plurality of data centers and a data synchronizing controller. The data synchronizing controller is communicatively coupled to the data centers for outputting a synchronizing command and a synchronizing parameter to the data centers periodically. One of the data centers adjusts a data transmitting condition thereof based on the synchronizing parameter so as to synchronize data to another one of the data centers such that each of the data centers has the same data.
    Type: Application
    Filed: April 13, 2015
    Publication date: June 2, 2016
    Inventors: Ming-Hsiao HSIEH, Chih-Chin YANG