Patents by Inventor Chih-Chong Wang

Chih-Chong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130232373
    Abstract: A method and apparatus for performing real time clock (RTC) calibration through frame number calculation are provided, where the method is applied to an electronic device. The method includes the steps of: before power failure of the electronic device occurs, obtaining an original time value from an RTC of the electronic device and storing the original time value and a frame number of a first frame into a storage unit; and after the electronic device is powered on since elimination of the power failure, obtaining a frame number of a second frame and performing at least one calculation operation according to the frame number of the second frame, the frame number of the first frame, and the original time value to determine a calibrated time value of the RTC, and updating the RTC with at least one of the calibrated time value and a derivative of the calibrated time value.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Inventors: Tung-Yi Wang, Chih-Chong Wang, Chun-Ming Kuo
  • Patent number: 7368785
    Abstract: A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field, therefore the transistor device has a relatively small size.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: May 6, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Li-Che Chen, Chih-Chong Wang
  • Publication number: 20080070369
    Abstract: A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field; therefore the transistor device has a relatively small size.
    Type: Application
    Filed: November 27, 2007
    Publication date: March 20, 2008
    Inventors: Li-Che Chen, Chih-Chong Wang
  • Publication number: 20060270171
    Abstract: A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field, therefore the transistor device has a relatively small size.
    Type: Application
    Filed: May 24, 2006
    Publication date: November 30, 2006
    Inventors: Li-Che Chen, Chih-Chong Wang
  • Patent number: 6621696
    Abstract: A non-screwed fastening device has a retaining ring and a shaft lever. The retaining ring has a first annular edge, an inner ring flange and a second annular edge. The first annular edge has a plurality of slits to make the retaining ring resilient and at least a groove located in the inner surface of the retaining ring. The inner ring flange is disposed in the surface region of the retaining ring for buckling the retaining ring and the shaft lever, and the second annular edge further has a recess region. The shaft lever has a first circular flute, a second circular flute, a first end portion and a second end portion. The first circular flute and the second circular flute are selectively buckled to the inner ring flange by the retaining ring resilience. One side region of the shaft lever having at least a lug is placed into the retaining ring along the groove and the first end portion is put into the locating hole of the peripheral device such that the lug is locked to the recess region for fastening.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: September 16, 2003
    Assignee: Quanta Computer, Inc.
    Inventor: Chih-Chong Wang
  • Publication number: 20030169565
    Abstract: A non-screwed fastening device has a retaining ring and a shaft lever. The retaining ring has a first annular edge, an inner ring flange and a second annular edge. The first annular edge has a plurality of slits to make the retaining ring resilient and at least a groove located in the inner surface of the retaining ring. The inner ring flange is disposed in the surface region of the retaining ring for buckling the retaining ring and the shaft lever, and the second annular edge further has a recess region. The shaft lever has a first circular flute, a second circular flute, a first end portion and a second end portion. The first circular flute and the second circular flute are selectively buckled to the inner ring flange by the retaining ring resilience. One side region of the shaft lever having at least a lug is placed into the retaining ring along the groove and the first end portion is put into the locating hole of the peripheral device such that the lug is locked to the recess region for fastening.
    Type: Application
    Filed: March 7, 2002
    Publication date: September 11, 2003
    Inventor: Chih-Chong Wang
  • Publication number: 20020162645
    Abstract: A heatsink assembly having a stabilization plate is described. The stabilization plate, such as an n-shaped PORON slice, is disposed under a heatsink, and is surrounding a thermal pad under the heatsink. The stabilization plate is helpful to stabilize the combination of the thermal pad up to the heatsink. With the stabilization, the thermal pad is efficiently stuck on to a die for dissipating the heat therefrom.
    Type: Application
    Filed: May 24, 2001
    Publication date: November 7, 2002
    Inventors: Chih-Chong Wang, Guo-Ming Huang, Hung-Chou Chan, Ming-Chu Hou
  • Patent number: 6042444
    Abstract: A method for fabricating a cathode of a field emission display. A doped polysilicon layer is formed over a substrate, and the doped polysilicon layer is patterned to form a plurality of field emitters. The doped polysilicon layer and the field emitters are patterned to form a plurality of field emission arrays. Then, a sharpening process is performed to form an oxide layer on the field emitters. A first dielectric layer and a second dielectric layer are formed conformal to the substrate, and a third dielectric layer is formed on the second dielectric layer. The third dielectric layer is planarized to expose the second dielectric layer on a top portion of each of the field emitters. The exposed second dielectric layer is removed, and an oxide layer is formed on the third dielectric layer and a top surface of the first dielectric layer on the top portion of the field emitter. A self-aligned metal layer is formed on the oxide layer.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: March 28, 2000
    Assignee: United Semiconductor Corp.
    Inventor: Chih-Chong Wang
  • Patent number: 5779514
    Abstract: A new fabrication technology for the chimney-shaped metal field emission elements with a self-alignment process which makes the emitter structure symmetrical. This tectnology is based on the isotropic or anisotropic, wet or dry etching and then the sputtering deposition of the emither material as well as the wet etching of attaching silicon. The finished field emitters are with excellent uniformity and high reproducibility and are able to emit the current thirty times in magnitude higher than that from the conventional cone-shaped field emitters at the same electric field.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: July 14, 1998
    Assignee: National Science Council
    Inventors: Huang-Chung Cheng, Chih-Chong Wang