Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A semiconductor device structure is provided. The semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. A second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. A contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. The first electric wall has a gradually decreasing width W5 towards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A de-glitch circuit, a de-glitch method and a short circuit protection device are provided. In a period during which a first flag signal is in a first logic state, the de-glitch circuit increases a counting result with a rising rate. In a period during which the first flag signal is in a second logic state, the de-glitch circuit decreases the counting result with a falling rate, wherein the rising rate is greater than the falling rate. The de-glitch circuit sets a logic state of a second flag signal according to a relationship between the counting result and a threshold.

Abstract: A de-glitch circuit, a de-glitch method and a short circuit protection device are provided. In a period during which a first flag signal is in a first logic state, the de-glitch circuit increases a counting result with a rising rate. In a period during which the first flag signal is in a second logic state, the de-glitch circuit decreases the counting result with a falling rate, wherein the rising rate is greater than the falling rate. The de-glitch circuit sets a logic state of a second flag signal according to a relationship between the counting result and a threshold.

Abstract: A short circuit detection circuit and a short circuit detection method for a multi-phase rectifier are provided, which are used for detecting conditions of a spectrum of a FWR signal outputted from the multi-phase rectifier in the frequency domain. Next, determining whether the detected signal indicating the amplitude of the frequency of the AC signal is greater than or equal to the reference signal, so as to determine whether the multi-phase rectifier has a short circuit condition. Therefore, the short circuit detection circuit and the short circuit detection method do not have any requirements for configuring a short circuit detection element on each current path of the multi-phase rectifier, so that the power loss and the cost can be reduced effectively.

Abstract: A short circuit detection circuit and a short circuit detection method for a multi-phase rectifier are provided, which are used for detecting conditions of a spectrum of a FWR signal outputted from the multi-phase rectifier in the frequency domain. Next, determining whether the detected signal indicating the amplitude of the frequency of the AC signal is greater than or equal to the reference signal, so as to determine whether the multi-phase rectifier has a short circuit condition. Therefore, the short circuit detection circuit and the short circuit detection method do not have any requirements for configuring a short circuit detection element on each current path of the multi-phase rectifier, so that the power loss and the cost can be reduced effectively.