Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.

Abstract: An antenna rotation structure includes a rotating shaft member rotatably disposed through a perforated groove of a housing, an annular member, and an elastic member. The rotating shaft member has a holding portion located in an accommodating space of the housing, a connecting portion connected to the holding portion and with an annular groove, and a gripping portion with one end connected to the connecting portion and the other end protruded from the housing. The annular member is disposed in the annular groove and abuts the perforated groove. The elastic member is sleeved on the one end of the gripping portion. The connecting portion and the one end of the gripping portion are disposed in the perforated groove. The gripping portion is turned to drive the rotating shaft member to rotate, thereby adjusting an angle of the antenna.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A waterproof container is adapted for an electronic device with a touch screen. The waterproof container includes an upper component and a lower component. The upper component includes a first layer, a second layer and a third layer. The second layer is disposed between the first layer and the third layer. A second touched part of the second layer is connected to a first touched part of the first layer by a plurality of first connections. The second touched part of the second layer is connected to a third touched part of the third layer by a plurality of second connections, and the plurality of first connections and the plurality of second connections are staggered relative to each other. The lower component is connected to the upper component. An accommodating space is enclosed by the lower component and the upper component for accommodating the electronic device.

Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

Abstract: Antenna rotation structure includes a rotating member and an angle adjusting member. The rotating member is rotatably disposed along an axial direction in an accommodating space of the housing and includes a holding portion and a pushing portion disposed at one side of the holding portion spaced apart from the axial direction. The angle adjusting member includes a pressing portion bonded to a through hole of the housing and made of an elastic material and, an abutting portion connected to the pressing portion and corresponding to the pushing portion. When the pressing portion is pressed by a force, it deforms and drives the abutting portion to push the pushing portion to drive the holding portion to rotate about the axial direction to adjust the angle of the antenna.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A light-emitting element panel, including a temporary storage substrate, an auxiliary pattern layer, multiple adhesive patterns, and multiple light-emitting elements, is provided. The auxiliary pattern layer is disposed on the temporary storage substrate and has multiple openings. The adhesive patterns are respectively disposed in the openings of the auxiliary pattern layer. The light-emitting elements are respectively disposed on the adhesive patterns. A reaction rate of the auxiliary pattern layer to a laser is lower than a reaction rate of the adhesive pattern to the laser. Moreover, another light-emitting element panel is also provided.

Abstract: An assembly structure of a transformer and a circuit board includes: a circuit board, a packaging chip, a transformer, a first conductive plate, a second conductive plate and a first heat sink. The packaging chip is disposed on the circuit board. The transformer has at least one first output electrode and at least one second output electrode connected to the first output electrode. The first conductive plate is disposed on the transformer and connected to the at least one first output electrode. The second conductive plate is disposed on the transformer and connected to the at least one second output electrode and the circuit board. The first heat sink is connected to the packaging chip and the first conductive plate, is disposed on the circuit board, and is connected to the circuit board and the first conductive plate.

Abstract: An assembly structure of a transformer and a circuit board includes: a circuit board, a packaging chip, a transformer, a first conductive plate, a second conductive plate and a first heat sink. The packaging chip is disposed on the circuit board. The transformer has at least one first output electrode and at least one second output electrode connected to the first output electrode. The first conductive plate is disposed on the transformer and connected to the at least one first output electrode. The second conductive plate is disposed on the transformer and connected to the at least one second output electrode and the circuit board. The first heat sink is connected to the packaging chip and the first conductive plate, is disposed on the circuit board, and is connected to the circuit board and the first conductive plate.

Abstract: A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel electrode. The active element includes a source, a gate, and a drain. The first dielectric layer is configured to cover the gate. The color filter unit is disposed above the first dielectric layer, and has an alignment opening. The second dielectric layer is disposed above the active element and the color filter unit, and has a contact hole. The pixel electrode is disposed above the second dielectric layer, and electrically connected to the drain through the contact hole. The contact hole of the second dielectric layer is located outside the alignment opening.

Abstract: A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel electrode. The active element includes a source, a gate, and a drain. The first dielectric layer is configured to cover the gate. The color filter unit is disposed above the first dielectric layer, and has an alignment opening. The second dielectric layer is disposed above the active element and the color filter unit, and has a contact hole. The pixel electrode is disposed above the second dielectric layer, and electrically connected to the drain through the contact hole. The contact hole of the second dielectric layer is located outside the alignment opening.

Abstract: A video data processing system comprises a control module coupled with a source module for receiving video data from the source module, the video data being associated with at least one source viewpoint; and a view adjustment module coupled with the control module for generating at least one adjusted viewpoint of the video data based on at least one of a set viewpoint number and a number of the at least one source viewpoint. The set viewpoint number is associated with at least one of a viewpoint number of at least one previously received video data and a viewpoint number of at least one previously coupled player module.

Abstract: A display panel includes a substrate having a display area and a blank area. The blank area includes at least one of a non-metal line region and a metal-line region. The non-metal line region includes a plurality of insulating patterns and a first conductive pattern layer formed on the substrate. The insulating patterns are isolated from each other by the first conductive pattern layer. The metal-line region includes an insulating multilayer formed on the substrate and a conductive pattern layer formed on the insulating multilayer. Several isolated zones are formed by the conductive pattern layer on the surface of the insulating multilayer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed thereon, an insulation layer disposed on the substrate and overlying the gate, a patterned semiconductor layer disposed on the insulation layer, a source and a drain disposed on the patterned semiconductor layer, a protective layer overlying the insulation layer, the source and the boundary of the drain to expose a portion of the drain, and a pixel electrode disposed on the substrate, overlying the protective layer overlying the boundary of the drain, electrically connected to the exposed drain.

Abstract: A method for fabricating a pixel unit is provided. A TFT is formed on a substrate. A protection layer and a patterned photoresist layer are sequentially formed on the substrate entirely. A patterned protection layer is formed by using the patterned photoresist layer as a mask and partially removing the protection layer, wherein the patterned protection layer has an undercut located at a sidewall thereof A pixel electrode material layer is formed to cover the substrate, the TFT and the patterned photoresist layer, wherein the electrode material layer is disconnected at the undercut and exposes the undercut. A pixel electrode electrically connected to the TFT is formed by lifting off the patterned photoresist layer and parts of the electrode material layer covering the patterned photoresist layer simultaneously through a stripper, wherein the stripper permeates from the undercut to an interface of the patterned photoresist layer and the patterned protection layer.