Patents by Inventor Chih-Chung Lu
Chih-Chung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990429Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.Type: GrantFiled: November 28, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Wu, Ying-Ching Shih, Kung-Chen Yeh, Li-Chung Kuo, Pu Wang, Szu-Wei Lu
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Publication number: 20240157217Abstract: A golf teaching method and a golf teaching system are provided. The golf teaching method includes: configuring image capturing devices and golf simulator to capture swing images and corresponding simulator data records, when a user performs a golf swing; configuring an expert model that includes expert motion information and corresponding correction suggestion information; configuring a computing device to perform an analysis process on the swing images and the simulator data records to divide the golf swing into user motions according to stages and obtaining records of user motion information corresponding to the plurality of stages, and to compare the user motion information with the corresponding expert motion information in each stage through the expert model, and to provide the corresponding correction suggestion information according to a comparison result; and configuring a user interface to provide the correction suggestion information.Type: ApplicationFiled: April 20, 2023Publication date: May 16, 2024Inventors: CHENG-HUNG TSAI, CHIA-YU JIH, CHIH-CHUNG CHIEN, LI-LIN LU, SHAO-JUN TAN, WEN-FU LAI
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Publication number: 20240162109Abstract: In an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.Type: ApplicationFiled: January 10, 2023Publication date: May 16, 2024Inventors: Hung-Yi Kuo, Chen-Hua Yu, Kuo-Chung Yee, Yu-Jen Lien, Ke-Han Shen, Wei-Kong Sheng, Chung-Shi Liu, Szu-Wei Lu, Tsung-Fu Tsai, Chung-Ju Lee, Chih-Ming Ke
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Patent number: 11967596Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.Type: GrantFiled: August 5, 2021Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
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Publication number: 20080094330Abstract: The present invention discloses a structure for storing overdrive image data and a method thereof, which divide image data into non-video data and video data and respectively store them in a non-video data storage region and a video data storage region of a memory unit, wherein the RGB data of the non-video data is directly stored in the video data storage region; the RGB data of the video data is transformed into YCbCr data; via checking a lookup table, the RGB data of the present video data is compared with the RGB data of the preceding frame to obtain overdrive YCbCr data; the YCbCr data and the overdrive YCbCr data are sampled, compressed and synthesized according to a video data compression standard and then stored in the video data storage region. Thereby, the memory space required by the overdrive technology can be reduced.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: Wei-Yeh Sun, Chih-Chung Lu
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Publication number: 20070291935Abstract: An apparatus for supporting advanced encryption standard encryption and decryption combines bytes substitution and inverse bytes substitution operations, and includes first and second matrix operation devices, first and second exclusive-OR operation modules, first and second multiplexers, and a table-look-up device. The first multiplexer selects one from the outputs of the first matrix operation device and first exclusive-OR operation module. The second multiplexer selects one from the outputs of the second matrix operation device and second exclusive-OR operation module. The table-look-up device applies a common look-up table so as to save operation resources. In addition, the elements of the encryption apparatus are connected in a way such that the entire critical paths and complexity are reduced, thus improving the speed of the apparatus.Type: ApplicationFiled: August 23, 2007Publication date: December 20, 2007Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Chih-Chung Lu
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Patent number: 7236593Abstract: An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multiplicative_inverse(x)+c while inverse byte substitution operation can be expressed as x=multiplicative_inverse(M?1*(y+c)), wherein M and M?1 are inverse matrix of each other and c is a constant matrix. Since the two equations employ a look-up table, that is, multiplicative_inverse(x), the lookup tables for use in byte substitution and inverse byte substitution operations are to be combined according to the invention so as to lower hardware complexity of the implementation. In addition, main operations of column mixing operation and inverse column mixing operation are to be rearranged to combine the two operations in part, resulting in simplified hardware implementation.Type: GrantFiled: March 29, 2002Date of Patent: June 26, 2007Assignee: Industrial Technology Research InstituteInventors: Chih-Chung Lu, Shau-Yin Tseng
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Publication number: 20060010486Abstract: A network security active detecting system for connecting to at least one client end and a server end in a network system includes a networking-judging unit for judging whether a networking request of a client end is sent to an authorized network, a security condition detecting unit for determining the security level of the client end after the networking-judging unit confirms the networking request of the client end is sent to the authorized network, a configuration exchange unit for controlling the client and server ends to negotiate for a communication protocol identified during the networking so as to determine a security service routine, a Layer 3 packet process unit for processing packets transmitted between the client end and the server end with the security service routine according to the communication protocol, and a negotiating mechanism for confirming the networking between the client and server ends for releasing system resources.Type: ApplicationFiled: November 16, 2004Publication date: January 12, 2006Inventors: Chih-Chung Lu, He-Ren Lin
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Publication number: 20050149746Abstract: A system for actively updating a cryptography module in a security gateway and related method is used in a security gateway, such as a VPN gateway according to an IPSEC protocol, which is connected between at least one user computer system and a network system. The system includes a Web GUI, a module update unit, a defined module unit, and an extended library. A user can easily update or add decryption/encryption modules into the extended library of the gateway through the Web GUI and the module update unit instead of updating the decryption/encryption modules along with the entire kernel firmware. This can reduce the setting time, increase the efficiency of operation, reduce the maintenance cost, and promote the expansion of decryption/encryption modules of the gateway so that network transmission can become much safer.Type: ApplicationFiled: May 19, 2004Publication date: July 7, 2005Inventors: Chih-Chung Lu, Hong-Wei Tzeng
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Publication number: 20050149721Abstract: A method of speeding up packet filtering that utilizes a search filter in compliance with the rules of the firewall, includes the following steps of presenting a mask characteristic value set in a first hash space with regard to all specific masks in need of being filtered in the firewall rules; presenting a packet characteristic value set in a second hash space with regard to each packet received by the firewall; performing a specific Boolean operation in use of the first and second hash spaces with the same size; and as long as the result of the specific Boolean operation determine that the packet characteristic value set is out of the mask characteristic value set, rapidly allowing the packet to pass through the firewall so as to reduce calculation time of all of the firewall rules, decrease system loading and prevent network congestion.Type: ApplicationFiled: May 5, 2004Publication date: July 7, 2005Inventor: Chih-Chung Lu
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Publication number: 20040202318Abstract: An apparatus for supporting advanced encryption standard encryption and decryption combines bytes substitution and inverse bytes substitution operations, and includes first and second matrix operation devices, first and second exclusive-OR operation modules, first and second multiplexers, and a table-look-up device. The first multiplexer selects one from the outputs of the first matrix operation device and first exclusive-OR operation module. The second multiplexer selects one from the outputs of the second matrix operation device and second exclusive-OR operation module. The table-look-up device applies a common look-up table so as to save operation resources. In addition, the elements of the encryption apparatus are connected in a way such that the entire critical paths and complexity are reduced, thus improving the speed of the apparatus.Type: ApplicationFiled: May 6, 2004Publication date: October 14, 2004Inventor: Chih-chung Lu
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Publication number: 20040125950Abstract: The present invention provides a method for protecting public key schemes from timing, power and fault attacks. In general, this is accomplished by implementing critical operations using “branchless” or fixed execution path routines whereby the execution path does not vary in any manner that can reveal new information about the secret key during subsequent operations. More particularly, the present invention provides a modular exponentiation algorithm without any redundant computation so that it can protect the secret key from C safe error attacks. The improved method also provides an algorithm that doesn't have a store operation with non-certain destination so that the secret key is immune from M safe error attacks.Type: ApplicationFiled: July 8, 2003Publication date: July 1, 2004Inventors: Sung-Ming Yen, Chih-Chung Lu, Shau-Yin Tseng
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Publication number: 20030099352Abstract: An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multiplicative_inverse(x)+c while inverse byte substitution operation can be expressed as x=multiplicative_inverse(M−1*(y+c)), wherein M and M−1 are inverse matrix of each other and c is a constant matrix. Since the two equations employ a look-up table, that is, multiplicative_inverse(x), the lookup tables for use in byte substitution and inverse byte substitution operations are to be combined according to the invention so as to lower hardware complexity of the implementation. In addition, main operations of column mixing operation and inverse column mixing operation are to be rearranged to combine the two operations in part, resulting in simplified hardware implementation.Type: ApplicationFiled: March 29, 2002Publication date: May 29, 2003Inventors: Chih-Chung Lu, Shau-Yin Tseng
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Publication number: 20020172355Abstract: There is disclosed a high-performance Booth-encoded Montgomery module for performing the computation of A*B*r−1 (mod N). A Booth encoder is provided for receiving two bits of A to perform a Booth encoding process, so as to produce a Booth code. A multiplicand selector is provided for receiving B and the Booth code so as to select a multiplicand. A first carry propagate adder is provided for adding the output of the multiplicand selector and a previous computation result to output. A multiplexer is provided for receiving four inputs 0, N, 2N, and 3N from a lookup table and selecting one of the inputs to output. A second carry propagate adder is provided for adding the outputs of the first carry propagate adder and the multiplexer to output. A shifter is provided for shifting the output from the second carry propagate adder to right by two bits, so as to produce a computation result.Type: ApplicationFiled: April 4, 2001Publication date: November 21, 2002Inventors: Chih-Chung Lu, An-Yeu Wu, Shau-Yin Tseng