Patents by Inventor Chih-Fan Huang
Chih-Fan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096800Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN
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Patent number: 11937515Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.Type: GrantFiled: August 9, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20240080180Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.Type: ApplicationFiled: December 20, 2022Publication date: March 7, 2024Inventors: Chih-Fan HSU, Wei-Chao CHEN, Jing-Lun Huang, Ming-Ching Chang, Feng-Hao Liu
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Patent number: 11923405Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.Type: GrantFiled: May 23, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11855022Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.Type: GrantFiled: June 30, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20230387183Abstract: Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.Type: ApplicationFiled: July 25, 2023Publication date: November 30, 2023Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11791371Abstract: Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.Type: GrantFiled: August 30, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20230317651Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.Type: ApplicationFiled: June 5, 2023Publication date: October 5, 2023Inventors: Chih-Fan Huang, Yen-Ming Chen, Chih-Sheng Li, Hui-Chi Chen, Chih-Hung Lu, Dian-Hau Chen
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Patent number: 11728375Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a first electrode layer formed over a substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure also includes a first dielectric layer formed on the first spacers, and an end of the first dielectric layer is in direct contact with the first pacer.Type: GrantFiled: June 13, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Fan Huang, Chih-Yang Pai, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11716910Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch slop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.Type: GrantFiled: August 25, 2020Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11670608Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.Type: GrantFiled: July 23, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hui-Chi Chen, Chih-Sheng Li, Chih-Hung Lu, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11664287Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.Type: GrantFiled: March 15, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
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Publication number: 20230062842Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Chih-Fan Huang, Wen-Chiung Tu, Liang-Wei Wang, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20230064385Abstract: Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20220384712Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20220359819Abstract: A method includes forming a magnetic tunnel junction (MTJ) stack over a substrate. The MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer. The method also includes patterning the top magnetic layer in a first etch process, after the patterning of the top magnetic layer depositing a spacer on sidewalls of the patterned top magnetic layer, and patterning the bottom magnetic layer in a second etch process.Type: ApplicationFiled: November 11, 2021Publication date: November 10, 2022Inventors: Chih-Fan Huang, Po-Sheng Lu, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20220359438Abstract: A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Fan HUANG, Mao-Nan WANG, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
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Publication number: 20220328440Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.Type: ApplicationFiled: June 30, 2022Publication date: October 13, 2022Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
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Publication number: 20220320265Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a first electrode layer formed over a substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure also includes a first dielectric layer formed on the first spacers, and an end of the first dielectric layer is in direct contact with the first pacer.Type: ApplicationFiled: June 13, 2022Publication date: October 6, 2022Inventors: Chih-Fan HUANG, Chih-Yang PAI, Yuan-Yang HSIAO, Tsung-Chieh HSIAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
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Publication number: 20220310903Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.Type: ApplicationFiled: July 16, 2021Publication date: September 29, 2022Inventors: Chih-Fan Huang, Kai-Wen Cheng, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen