Patents by Inventor Chih-Fei Lee

Chih-Fei Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901305
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Publication number: 20230369517
    Abstract: An image sensor device includes nanostructures for improving light absorption efficiency. The image sensor device includes a substrate, a light absorption region, and a nanostructure array. The light absorption region is over the substrate. The nanostructure array us over the light absorption region. The nanostructure array includes a plurality of nanostructures repeatedly arranged from a top view.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
  • Patent number: 11777040
    Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Publication number: 20230106960
    Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.
    Type: Application
    Filed: November 28, 2022
    Publication date: April 6, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
  • Patent number: 11515435
    Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Publication number: 20220310528
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO
  • Patent number: 11362039
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 14, 2022
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Publication number: 20210028318
    Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
  • Publication number: 20210028120
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO
  • Patent number: 10804211
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Patent number: 10804414
    Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Publication number: 20190252559
    Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Patent number: 10269990
    Abstract: A semiconductor device is provided, which includes a substrate and at least one nanostructure. The substrate has sensing pixels, and each of the sensing pixels has a photo sensing region for absorbing incident light. The nanostructure is directly on the photo sensing region. The nanostructure of each of the sensing pixels has a projected portion on an upper surface of the substrate, and a circle equivalent diameter of the projected portion of the nanostructure of each of the sensing pixels is substantially within a wavelength range of 100 nm to 1900 nm of the incident light configured to enter the substrate through the nanostructure.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Patent number: 10134694
    Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fei Lee, Fu-Cheng Chang, Chi-Cherng Jeng, Hsin-Chi Chen, Yuan-Ko Hwang
  • Publication number: 20180323152
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO
  • Patent number: 10115758
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Patent number: 10020265
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Publication number: 20180166476
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 14, 2018
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Publication number: 20180166592
    Abstract: A semiconductor device is provided, which includes a substrate and at least one nanostructure. The substrate has sensing pixels, and each of the sensing pixels has a photo sensing region for absorbing incident light. The nanostructure is directly on the photo sensing region. The nanostructure of each of the sensing pixels has a projected portion on an upper surface of the substrate, and a circle equivalent diameter of the projected portion of the nanostructure of each of the sensing pixels is substantially within a wavelength range of 100 nm to 1900 nm of the incident light configured to enter the substrate through the nanostructure.
    Type: Application
    Filed: March 27, 2017
    Publication date: June 14, 2018
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Publication number: 20170179037
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: May 18, 2016
    Publication date: June 22, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO