Patents by Inventor Chih-Fen CHEN
Chih-Fen CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126861Abstract: A device unlocking method and an electronic device are provided. The method includes: detecting fingerprint information of a user by a first sensor of the electronic device; authenticating the fingerprint information and temporarily storing an authentication result of the fingerprint information; after authenticating the fingerprint information, detecting operation environment information related to the electronic device by a second sensor of the electronic device; and in response to the operation environment information meeting a default condition, unlocking the electronic device according to the authentication result.Type: ApplicationFiled: May 9, 2023Publication date: April 18, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chih-Hsien Yang, Hui-Fen Chen, I-Hsi Wu
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Patent number: 11610825Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).Type: GrantFiled: October 26, 2020Date of Patent: March 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng
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Patent number: 11411108Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: GrantFiled: October 23, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
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Publication number: 20210043771Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen CHEN, Chui-Ya PENG, Ching YU, Pin-Hen LIN, Yen CHUANG, Yuh-Ta FAN
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Publication number: 20210043524Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng
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Patent number: 10818563Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).Type: GrantFiled: November 26, 2019Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng
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Patent number: 10818790Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: GrantFiled: June 7, 2019Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
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Publication number: 20200098650Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng
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Patent number: 10515861Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.Type: GrantFiled: March 29, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng
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Publication number: 20190312144Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.Type: ApplicationFiled: June 7, 2019Publication date: October 10, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen CHEN, Chui-Ya PENG, Ching YU, Pin-Hen LIN, Yen CHUANG, Yuh-Ta FAN
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Patent number: 10319857Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.Type: GrantFiled: October 30, 2017Date of Patent: June 11, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
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Publication number: 20190035697Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.Type: ApplicationFiled: March 29, 2018Publication date: January 31, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng
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Publication number: 20180069120Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.Type: ApplicationFiled: October 30, 2017Publication date: March 8, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen CHEN, Chui-Ya PENG, Ching YU, Pin-Hen LIN, Yen CHUANG, Yuh-Ta FAN
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Patent number: 9812570Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.Type: GrantFiled: June 30, 2015Date of Patent: November 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
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Patent number: 9780209Abstract: A semiconductor device includes a substrate, a gate stack, at least one epitaxy structure, a dielectric material, and a contact. The gate stack is present on the substrate. The gate spacer is present on a sidewall of the gate stack. The epitaxy structure is partially present in the substrate. The dielectric material is present on the substrate and between the epitaxy structure and the gate spacer. The contact is present on the epitaxy structure, the dielectric material, and the gate spacer.Type: GrantFiled: July 13, 2016Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fen Chen, Bang-Yu Huang, Chui-Ya Peng
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Publication number: 20170005196Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Chih-Fen CHEN, Chui-Ya PENG, Ching YU, Pin-Hen LIN, Yen CHUANG, Yuh-Ta FAN