Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Abstract: An antenna rotation structure includes a rotating shaft member rotatably disposed through a perforated groove of a housing, an annular member, and an elastic member. The rotating shaft member has a holding portion located in an accommodating space of the housing, a connecting portion connected to the holding portion and with an annular groove, and a gripping portion with one end connected to the connecting portion and the other end protruded from the housing. The annular member is disposed in the annular groove and abuts the perforated groove. The elastic member is sleeved on the one end of the gripping portion. The connecting portion and the one end of the gripping portion are disposed in the perforated groove. The gripping portion is turned to drive the rotating shaft member to rotate, thereby adjusting an angle of the antenna.

Abstract: The control circuit for controlling a display panel is provided. The control circuit includes a first driving circuit and a second driving circuit for driving the display panel. The first driving circuit includes first output terminals and first input terminals. The first driving circuit outputs a plurality of test signals to the first output terminals sequentially during different periods in a diagnosis stage. The second driving circuit includes second input terminals and second output terminals. The second driving circuit receives the test signals through the second input terminals in the diagnosis stage, and outputs a plurality of response signals to the second output terminals sequentially during different periods in response to the test signals. The first driving circuit receives the response signals through the first input terminals, and judges a connecting status of the first driving circuit and the second driving circuit according to the response signals.

Abstract: System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.

Abstract: A package structure includes a first carrier, a second carrier, and a first electronic device. The first carrier is electrically connected to a first voltage. The second carrier includes a first substrate and a first interconnect structure. The first substrate is in contact with the first carrier, the first interconnect structure is electrically connected to a second voltage, and the first interconnect structure and the first carrier are deposited on two opposite sides of the first substrate. The first electronic device is deposited on the first interconnect structure and away from the first carrier. The first electronic device is in contact with the first interconnect structure.

Abstract: Antenna rotation structure includes a rotating member and an angle adjusting member. The rotating member is rotatably disposed along an axial direction in an accommodating space of the housing and includes a holding portion and a pushing portion disposed at one side of the holding portion spaced apart from the axial direction. The angle adjusting member includes a pressing portion bonded to a through hole of the housing and made of an elastic material and, an abutting portion connected to the pressing portion and corresponding to the pushing portion. When the pressing portion is pressed by a force, it deforms and drives the abutting portion to push the pushing portion to drive the holding portion to rotate about the axial direction to adjust the angle of the antenna.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A random-number-generating circuit is provided, which includes a noise-voltage generator, a voltage-controlled oscillator, a ring oscillator, and a D flip-flop (DFF). The noise-voltage generator converts an external voltage into a noise voltage. The voltage-controlled oscillator receives the noise voltage, and generates a first clock signal according to the noise voltage. The ring oscillator generates a sampling clock signal. The DFF receives the first clock signal, and samples the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

Abstract: A low-dropout regulator including a first comparator, an edge trigger, a second comparator, a third comparator, and an output stage circuit is provided. The first comparator generates a first comparison signal according to a first reference signal and an output signal. The edge trigger outputs a trigger signal according to the first comparison signal, a second comparison signal, and a third comparison signal. The second comparator generates the second comparison signal according to the output signal and a second reference signal. The third comparator generates the third comparison signal according to the output signal and a third reference signal. The output stage circuit outputs the output signal according to the first comparison signal, the second comparison signal, and the third comparison signal. The output stage circuit includes a plurality of hysteresis controllers and a plurality of power transistors. Each hysteresis controller controls a conduction state of a corresponding power transistor.

Abstract: An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.

Abstract: Disclosed is a power control system with zero voltage switching including a power controller, a rectification unit, a power unit, a transformer unit, a primary side switch unit, a current sensing unit, an auxiliary switch unit, an output unit, and a current sensing unit for implementing a function of flyback power conversion. The power controller has a power pin, a ground pin, a primary side driving pin, a voltage sensing pin, an auxiliary driving pin, and an auxiliary winding sensing pin, In particular, the auxiliary switch unit is controlled to influence an primary side winding through an auxiliary winding so as to reduce the drain voltage of the primary side switch unit. Further, the primary side switch unit is turned on when the drain voltage is decreased to the lowest value, thereby greatly reducing switching loss and increasing efficiency of power conversion.

Abstract: A multi-channel memory device includes N first memory blocks, a first redundancy memory block, and N first interface circuits. Each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block. The first interface circuits respectively select N first selected memory blocks in the first memory block and the first redundancy memory block according to a plurality of first selection signals, where N is a positive integer greater than 1.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Abstract: A slim-type gas transportation device includes a slim-type gas pump and a slim-type valve structure. The slim-type valve structure includes a first thin plate, a valve frame, a valve plate and a second thin plate. The first thin plate has a hollow portion. The valve plate is disposed within an accommodation space of the valve frame. The valve plate includes a valve opening. The valve opening is not aligned with the hollow portion. The second thin plate includes a gas outlet surface, a pressure relief surface, a gas outlet groove, an outlet aperture, a pressure relief hole and a pressure relief trench. The outlet aperture is hollowed out from the gas outlet groove to the pressure relief surface and corresponding in position to the valve opening. The pressure relief hole is spaced apart from the gas outlet groove. The pressure relief trench is concavely formed from the pressure relief surface.

Abstract: System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.