Abstract: A motor stator has an annular stator core, and a plurality of tooth portions spaced on the inner surface of the annular stator core which has a slot formed on each of two sides of each of the tooth portions. Each of the tooth portions has a coil wound and a portion of the coil is located in the two slots of each of the tooth portions. Each of the coils is formed by a metal wire coiled around a bobbin several times from the inner side to the outer side. The bobbin has an inner guide frame and an outer guide frame, both of them have a structure with a bottom plate and a side plate that are arranged vertically so that the coil can be attached to the bobbin to miniaturize the motor stator.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: Manufacturing of a shoe or a portion of a shoe is enhanced by executing various shoe-manufacturing processes in an automated fashion. For example, information describing a shoe part may be determined, such as an identification, an orientation, a color, a surface topography, an alignment, a size, etc. Based on the information describing the shoe part, automated shoe-manufacturing apparatuses may be instructed to apply various shoe-manufacturing processes to the shoe part, such as a pickup and placement of the shoe part with a pickup tool.

Abstract: A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.

Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A recursive discrete Fourier transform (RDFT) of this invention uses an input-decimation technique to reduce the number of input sequences for a recursive-filter so as to decrease the computation cycle of the recursive-filter. Therefore, the time complexity of the RDFT can be minimized, namely, increasing the throughput of the RDFT.

Abstract: A recursive discrete Fourier transform (RDFT) of this invention uses an input-decimation technique to reduce the number of input sequences for a recursive-filter so as to decrease the computation cycle of the recursive-filter. Therefore, the time complexity of the RDFT can be minimized, namely, increasing the throughput of the RDFT.

Abstract: A joint carrier synchronization and channel equalization method for OFDM systems, that is suitable for use in a receiver of said orthogonal frequency division multiplexer (OFDM) systems, comprising the following steps: firstly, receiving a reception signal sample of an OFDM symbol, and obtaining simultaneously a phase error and a gain error on each sub-channel in a frequency domain, through outputting a sub-channel signal on each said sub-channel in said frequency domain; next, obtaining an execution carrier frequency offset factor, an execution phase compensation factor, and an execution gain compensation factor based on said phase error and said gain error; and finally, eliminating a phase offset of said reception signal sample of a next symbol in a time domain based on said factors, and compensating a magnitude distortion and a phase distortion on each said sub-channel in said frequency domain for said reception signal of said next symbol.

Abstract: A joint carrier synchronization and channel equalization method for OFDM systems, that is suitable for use in a receiver of said orthogonal frequency division multiplexer (OFDM) systems, comprising the following steps: firstly, receiving a reception signal sample of an OFDM symbol, and obtaining simultaneously a phase error and a gain error on each sub-channel in a frequency domain, through outputting a sub-channel signal on each said sub-channel in said frequency domain; next, obtaining an execution carrier frequency offset factor, an execution phase compensation factor, and an execution gain compensation factor based on said phase error and said gain error; and finally, eliminating a phase offset of said reception signal sample of a next symbol in a time domain based on said factors, and compensating a magnitude distortion and a phase distortion on each said sub-channel in said frequency domain for said reception signal of said next symbol.

Abstract: An efficient method for calculating the step-sizes for a frequency-domain equalizer of a discrete-multitone communications system using signal power estimation and tone grouping (SPE-TG) while on-line. The SPE-TG method is used to calculate a plurality of subchannel step-sizes which are then stored in a lookup table. When on-line, the method uses signal power estimation to select step sizes for each tone, and uses these step sizes for frequency domain equalization. The SPE-TG method simplifies the calculations necessary for frequency domain equalization, thereby saving significant hardware and/or processing resources. The SPE-TG method is reliable and robust, and does not depend upon assumptions about the line, location, or channel.

Abstract: A discrete multi-tone (DMT) communication system is provided herein, replacing the conventional inversed discrete Fourier transform (IDFT) and DFT with IDHT (together with the complex-to-real transformation) and a DHT alone respectively at the transmitting end and the receiving end. A DHT-based frequency-domain equalizer (FEQ) at the receiving end equalizes each of the 0-th to (N?1)-th DHT subchannels, where N is the number of point of the DHT. Finally, each of the 0-th to ( N 2 - 1 ) - th subchannels of the DMT system is obtained by combining the k-th and (N-k)-th subchannels of the DHT-based FEQ for k=0, 1, . . . , ( N 2 - 1 ) .

Abstract: A discrete multi-tone (DMT) communication system is provided herein, replacing the conventional inversed discrete Fourier transform (IDFT) and DFT with IDHT (together with the complex-to-real transformation) and a DHT alone respectively at the transmitting end and the receiving end. A DHT-based frequency-domain equalizer (FEQ) at the receiving end equalizes each of the 0-th to (N?1)-th DHT subchannels, where N is the number of point of the DHT. Finally, each of the 0-th to (N/2?1)-th subchannels of the DMT system is obtained by combining the k-th and (N-k)-th subchannels of the DHT-based FEQ for k=0, 1, . . . , (N/2?1).

Abstract: An efficient method for calculating the step-sizes for a frequency-domain equalizer of a discrete-multitone communications system using signal power estimation and tone grouping (SPE-TG) while on-line. The SPE-TG method is used to calculate a plurality of subchannel step-sizes which are then stored in a lookup table. When on-line, the method uses signal power estimation to select step sizes for each tone, and uses these step sizes for frequency domain equalization. The SPE-TG method simplifies the calculations necessary for frequency domain equalization, thereby saving significant hardware and/or processing resources. The SPE-TG method is reliable and robust, and does not depend upon assumptions about the line, location, or channel.

Abstract: An equalizing device includes a first filter, a target filter, an error determining device coupled with the first filter and the target filter, and a coefficient processor coupled with the error determining device. The first filter has a first set of coefficients and processes input signals transmitted through a communication channel to reduce channel response. The target filter has a second set of coefficients and generates a target channel output. The error determining device then processes an output of the first filter and the target channel output to generate error signals. The coefficient processor maintains constant at least one coefficient of the first or the second sets of coefficients and updates the remaining coefficients of the first and the second sets of coefficients based on the error signals.