Abstract: A component housing insertable in a chassis for a computing device blocking air flow when in a pulled out position is disclosed. The component housing has a front end and an opposite rear end. A pair of side walls are provided between the front end and the rear end. The side walls are slidably connected to the chassis to allow the component housing to be moved between an inserted position and the pulled-out position. A cover on the rear end has an open position allowing air flow through the rear end when the component housing is in the inserted position. The cover has a closed position blocking air flow through the aperture when the component housing is in the pulled out position.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A removable lever apparatus for inserting and removing computer equipment from a chassis module of a server rack includes a central rotatable structure, a long arm connected to and extending in a first direction away from the central rotatable structure, and a short arm connected to and extending in a second direction away from the central rotatable structure. The central rotatable structure includes a rotation stopper for limiting rotation about the axis of rotation between an inserting position and a removing position. The central rotatable structure also includes a retention structure for maintaining the coupling to the tray when the central rotatable structure is in a position other than the inserting position. The short arm is configured to engage a side wall of the chassis module when the central rotatable structure is rotated.

Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

Abstract: An implant guide system for hip replacement surgery includes an angle guide member and a first positioning plate. The angle guide member has a body and a protrusion that are substantially connected to each other. The body has a curved surface corresponding in shape to a surface of a patient's acetabulum. The protrusion has a first through hole extending to the body. An acute angle is defined between an extension line of the first through hole and a flat surface of the body. The first positioning plate has a first holding portion and a first spacing portion that are substantially connected to each other. The first spacing portion has a second through hole, a third through hole and a fourth through hole that are parallel to each other.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain contact structure formed over a semiconductor substrate, and a first gate stack formed over the semiconductor substrate and adjacent to the source/drain contact structure. The semiconductor device structure also includes an insulating cap structure formed over and separated from an upper surface of the first gate stack. In addition, the semiconductor device structure includes first gate spacers formed over opposing sidewalls of the first gate stack to separate the first gate stack from the source/drain contact structure. The first gate spacers extend over opposing sidewalls of the insulating cap structure, so as to form an air gap surrounded by the first gate spacers, the first gate stack, and the insulating cap structure.

Abstract: A component housing insertable in a chassis for a computing device blocking air flow when in a pulled out position is disclosed. The component housing has a front end and an opposite rear end. A pair of side walls are provided between the front end and the rear end. The side walls are slidably connected to the chassis to allow the component housing to be moved between an inserted position and the pulled-out position. A cover on the rear end has an open position allowing air flow through the rear end when the component housing is in the inserted position. The cover has a closed position blocking air flow through the aperture when the component housing is in the pulled out position.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: An air baffle insertable between a chassis wall and a computer component such as a GPU and heat sink mounted on a GPU tray to divert air flow to the computer component is disclosed. The air baffle includes a single sheet having a bottom panel, a top panel, and a pair of parallel side walls. Each of the parallel side walls are connected to the bottom and top panels. A first end wall is joined to the side walls and the top and bottom panel. The first end wall directs air flow toward the computer component.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.

Abstract: A cover for covering an opening of a socket formed by a housing comprises a body; one or more bosses extending from the body, a first locking mechanism, a second locking mechanism, and a release tab. The bosses movably couple the body to the housing such that the body is movable between first and second positions. The first locking mechanism releasably attaches to the housing to secure the body in the first position. The second locking mechanism releasably attaches to the housing to secure the body in the second position. The release tab aids in detaching the first locking mechanism from the first wall and the second locking mechanism from the second wall. When the body is in the first position, the body allows access to the socket through the opening. When the body is in the second position, the body prevents access to the socket through the opening.

Abstract: A release mechanism is disclosed that can facilitate safely and efficiently removing an expansion card from a computing device. The release mechanism can be installed on a motherboard around an expansion slot, and can include an opening that permits access to the expansion slot to allow an expansion card to be installed therein. When removal of the expansion card is desired, a handled of the release mechanism can be pulled, causing contact surfaces of the release mechanism to push the expansion card away from the expansion slot with even force, removing the need to tilt the expansion card.

Abstract: An air baffle insertable between a chassis wall and a computer component such as a GPU and heat sink mounted on a GPU tray to divert air flow to the computer component is disclosed. The air baffle includes a single sheet having a bottom panel, a top panel, and a pair of parallel side walls. Each of the parallel side walls are connected to the bottom and top panels. A first end wall is joined to the side walls and the top and bottom panel. The first end wall directs air flow toward the computer component.

Abstract: A package structure includes a redistribution layer (RDL) structure, a die, and an encapsulant. The die is attached to the RDL structure through an adhesive layer. The encapsulant is disposed on the RDL structure and laterally encapsulates the die and the adhesive layer. The encapsulant includes a protruding part extending into the RDL structure and having a bottom surface in contact with the RDL structure.

Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: Various examples are provided related to surfaces that can achieve controllable dynamic iridescence. In one example, a magnetically actuated surface includes an array of magnetic nanopillars; and a ferrofluid sealed in a microfluidic channel over the array of magnetic nanopillars. In another example, a method for forming a magnetically actuated surface includes generating a 2D periodic array of recesses in a photoresist layer; generating a nanopillar template from the 2D periodic array of recesses in the photoresist layer; forming a microfluidic channel over the nanopillar template; and filling the microfluidic channel with a ferrofluid comprising magnetic nanoparticles in a fluid medium.