Patents by Inventor Chih-Hao Lin

Chih-Hao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240068124
    Abstract: An apparatus for producing silicon carbide crystal is provided and includes a composite structure formed by a plurality of graphite layers and silicon carbide seed crystals, wherein a density or thickness of each layer of graphite is gradually adjusted to reduce a difference of a thermal expansion coefficient and Young's modulus between the graphite layers and silicon carbide. The composite structure can be stabilized on a top portion or an upper cover of a crucible made of graphite, thereby preventing the silicon carbide crystal from falling off.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 29, 2024
    Inventors: CHIH-LUNG LIN, PO-FEI YANG, CHIE-SHENG LIU, CHUNG-HAO LIN, HSIN-CHEN YEH, HAO-WEN WU
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240055264
    Abstract: Provided is a wafer polishing method comprising: a step of determining a first correlation a second correlation; a step of calculating mechanical polishing rate/chemical polishing rate; a step of obtaining a relationship between the ratio of the mechanical polishing rate to the chemical polishing rate and one or more indications of wafer flatness and determining a specific range of the ratio of the mechanical polishing rate to the chemical polishing rate; a step of selecting a first target polishing solution that meets the specific range of the ratio of the mechanical polishing rate to the chemical polishing rate based on the first correlation and the second correlation; and a step of polishing wafers using the first target polishing solution. Also provided is a wafer production method including a step of performing a polishing process by the above wafer polishing method.
    Type: Application
    Filed: October 28, 2021
    Publication date: February 15, 2024
    Applicant: SUMCO Corporation
    Inventors: Chih Hao LIN, Kazushige TAKAISHI
  • Patent number: 11892158
    Abstract: A light source device includes first and second laser light sources, a wavelength conversion unit, a light condensing module, a light combining member, and light guiding members. The first laser light source is configured to emit a first light beam along a first axis. The second laser light source is arranged along the second axis with the first laser light source and configured to emit a second light beam along the first axis. The wavelength conversion unit is configured to convert the second light beam into a color light. The condensing module is configured to condense the color light. The light combining member is configured to receive the first light beam and the color light. The light guiding members are configured to guide at least one of the first light beam and the color light.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: February 6, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Chih-Hao Lin
  • Publication number: 20240012319
    Abstract: An illumination system for a projector includes a light engine module, a light source module, a reflective mirror, a beam splitter, a phosphor wheel, and a lens assembly. The light source module can emit blue light along a first direction. The reflective mirror may reflect the blue light such that the blue light transmits in a second direction. A reflective region of the phosphor wheel can reflect a first portion of the blue light, and a first wavelength conversion region of the phosphor wheel can to activate a second portion of the blue light to form first band light. The lens assembly is configured to allow the first band light to pass through. The reflective region of the beam splitter is configured to reflect the first portion of the blue light and the first band light to the light engine module along the first direction.
    Type: Application
    Filed: October 18, 2022
    Publication date: January 11, 2024
    Inventor: Chih-Hao LIN
  • Publication number: 20240011620
    Abstract: A light source device includes first and second laser light sources, a wavelength conversion unit, a light condensing module, a light combining member, and light guiding members. The first laser light source is configured to emit a first light beam along a first axis. The second laser light source is arranged along the second axis with the first laser light source and configured to emit a second light beam along the first axis. The wavelength conversion unit is configured to convert the second light beam into a color light. The condensing module is configured to condense the color light. The light combining member is configured to receive the first light beam and the color light. The light guiding members are configured to guide at least one of the first light beam and the color light.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 11, 2024
    Inventor: Chih-Hao LIN
  • Patent number: 11786393
    Abstract: An ostomy pouching device for the removal of biological waste from a patient. An embodiment of an ostomy pouching device includes an outer container housing an inner bag for receiving waste from a patient's bowel. The device includes a bowel connector to connect the bowel to the inner bag. The outer container includes an air exit aperture through which air may exit the container as it is displaced as the inner bag expands, and a gas tunnel for removing gas from the inner bag.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 17, 2023
    Inventors: Chih-Hao Lin, Wan-Chen Shen, Wei-Ting Shih
  • Patent number: 11773222
    Abstract: A curable composition and an electronic device employing the same are provided. The curable composition includes 100 parts by mole of a first siloxane compound represented by Formula (I) wherein n is 8 to 232, wherein R1 is independently C1-3 alkyl group; 1 to 15 parts by mole of a second siloxane compound represented by Formula (II) wherein x?2, y?2, and x/y is between 0.1 and 3, and R2, R3 and R4 are independently C1-3 alkyl group; 1 to 15 parts by mole of a third siloxane compound represented by Formula (III) and 90 to 250 parts by mole of a curing agent represented by Formula (IV) wherein m is 7 to 230, wherein R5 is independently C1-3 alkyl group.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: October 3, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Hao Lin, Yueh-Chuan Huang, Kai-Chi Chen, Wen-Bin Chen
  • Patent number: 11759858
    Abstract: A method for manufacturing a metal object having a solid lubricating surface layer includes: providing a metal blank having a surface; providing a plurality of microparticles and solid lubricating powder, and mixing them together, wherein the microparticles have a hardness greater than that of the surface; and projecting the microparticles and the solid lubricating powder onto the surface, wherein the microparticles cause plastic flow on the surface to form a compressive stress layer, and the solid lubricating powder adheres to the compressive stress layer to form a solid lubricating surface layer.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: September 19, 2023
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Tseng-Jen Cheng, Kai-Han Chen, Fu-Chuan Hsu, Chih-Hao Lin
  • Patent number: 11734054
    Abstract: In various embodiments, a function build application compiles source code to generate an executable version of a function that has a first function signature. The function build application then replaces a first data type of a first parameter included in the first function signature with a second data type to generate a second function signature for a client stub function. Subsequently, the function build application generates a remote procedure call (RPC) client that includes the client stub function. Notably, the RPC client causes the function to execute when the client stub function is invoked. Advantageously, unlike conventional techniques that require manual generation of strongly typed functions, the function build application automatically customizes the RPC client for the function.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 22, 2023
    Assignee: NETFLIX, INC.
    Inventors: Francisco J San Miguel, Ameya Vasani, Dmitry Vasilyev, Chih Hao Lin, Xiaomei Liu, Naveen Mareddy, Guanhua Ye, Megha Manohara, Anush Moorthy
  • Publication number: 20230261165
    Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 17, 2023
    Inventors: Chih-Hao LIN, Jo-Hsiang CHEN, Shih-Lun LAI, Min-Che TSAI, Jian-Chin LIANG
  • Patent number: 11729968
    Abstract: A method for manufacturing a dynamic random access memory includes: forming a buried bit line in a substrate; forming a plurality of buried word lines in the substrate, wherein the bottom surfaces of the buried word lines are higher than the top surface of the buried bit line; forming a bit line contact structure on the buried bit line; forming a through hole passing through the bit line contact structure, wherein the bit line contact structure is not in direct contact with the buried bit line, and the material of the bit line contact structure is different from the material of the buried bit line; forming a conductive plug between the bit line contact structure and the buried bit line; and forming a capacitor structure on the substrate.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: August 15, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Chih-Hao Lin
  • Publication number: 20230234933
    Abstract: An epoxy compound, composition and cured product thereof are provided. The epoxy compound has a structure represented by Formula (I) wherein R1 and R2 are each independently cyano group, isocyanate group, oxiranyl, methyloxiranyl group, glycidyl group, methylglycidyl group, epoxypropyl group, oxetanyl group, oxetanemethyl group, or C1-C10 alkoxy group; Z is —O—, R3 and R4 are each independently hydrogen, fluorine, methyl, fluoromethyl, or ethyl; n and m are each independently 3, 4, 5, 6, 7, 8, 9, or 10; and i and j are each independently 1, 2, or 3.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 27, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Meei-Yu HSU, Chih-Hao LIN, Kai-Chi CHEN
  • Publication number: 20230238362
    Abstract: A light-emitting diode (LED) display device, including a substrate, a de-mura region, a plurality of mounting blocks, a first LED chip array and a second LED chip array, is disclosed. The substrate includes a first region and a second region adjacent to each other. The de-mura region includes part of the first region and part of the second region. The mounting blocks are arranged in the first and the second region as an array, each mounting block including a first and a second mounting part. The first and the second mounting part are connected in parallel. The first LED chip array includes multiple first LED chips. The second LED chip array includes multiple second LED chips. Each first mounting part is arranged on the first side of the corresponding mounting block, and each second mounting part is arranged on the second side of the corresponding mounting block.
    Type: Application
    Filed: January 26, 2022
    Publication date: July 27, 2023
    Inventors: Jian-Chin LIANG, Chih-Hao LIN, Wei-Yuan MA, Jo-Hsiang CHEN
  • Patent number: 11705495
    Abstract: Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: July 18, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Yi-Tsung Tsai, Chih-Hao Lin
  • Publication number: 20230223386
    Abstract: An inorganic light-emitting device is provided. The inorganic light-emitting device includes a carrier; a plurality of green chips, a plurality of red chips, and a plurality of blue chips periodically arranged on the carrier. The number of green chips is greater than the number of red chips, and the number of green chips is greater than the number of blue chips. A minimum distance Psub_g between adjacent ones of the green chips is smaller than a minimum distance Psub_r between adjacent ones of the red chips in a first direction D1, and the minimum distance Psub_g between adjacent ones of the green chips is smaller than a minimum distance Psub_b between adjacent ones of the blue chips in the first direction D1.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 13, 2023
    Inventors: Chih-Hao LIN, Jian-Chin LIANG, Jui-Yi WU
  • Patent number: 11699673
    Abstract: A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: July 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
  • Publication number: 20230215011
    Abstract: A panoramic video conference system and method are provided. The panoramic video conference system includes a panoramic video generating apparatus and a control apparatus. The control apparatus analyzes a panoramic video to identify a plurality of video objects in the panoramic video. The control apparatus selects a video object to be removed from the video objects based on a privacy mode. The control apparatus removes a video corresponding to the video object. The control apparatus generates a panoramic conference video based on the panoramic video and a background filling video.
    Type: Application
    Filed: April 10, 2022
    Publication date: July 6, 2023
    Inventors: Kuo Chih LO, Chih Hao LIN
  • Publication number: 20230178523
    Abstract: A light-emitting diode display panel includes a driving substrate, and a first light-emitting region and a second light-emitting region disposed on the driving substrate. The first light-emitting region has a first region and a second region adjacent to the first region in the first direction. The second light-emitting region is adjacent to the first light-emitting region and has a first corresponding region. The second region is between the first region and the first corresponding region. The light-emitting diode display panel further includes pixels disposed in the first region, the second region, and the first corresponding region. Each pixel includes a first light-emitting unit. The first pitch is between the first light-emitting units in the first region and in the second region. The second pitch is between the first light-emitting units in the second region and the first corresponding region. The first pitch is shorter than the second pitch.
    Type: Application
    Filed: August 22, 2022
    Publication date: June 8, 2023
    Inventors: Chih-Hao LIN, Wei-Yuan MA, Jo-Hsiang CHEN