Abstract: A power bank has a station and a plurality of battery modules. When the battery modules are stacked on the station, rechargeable batteries of the battery modules are electrically connected in parallel. When a charging port of the station is electrically connected to an external power supply, a charging-discharging control circuit of the station receives electric energy from the external power supply via the charging port and uses the received electric energy to charge the rechargeable batteries. When a discharging port of the station is electrically connected to an external electronic device, the charging-discharging control circuit transfers electric energy received from the rechargeable batteries to the external electronic device. Each of the battery modules is replaceable, and the total number of the battery modules of the power bank is adjustable.

Abstract: A power bank has a station and a plurality of battery modules. Each of the battery modules can be positioned in a corresponding slot of the station in a pluggable way and is electrically connected to a charging-discharging control circuit of the station. When a main charging port of the station is electrically connected to a power supply, the charging-discharging control circuit receives electric power from the power supply via the main charging port and uses the received electric power to charge rechargeable batteries of the battery modules. When a main discharging port of the station is electrically connected to an electronic apparatus, the charging-discharging control circuit receives electric power from the rechargeable batteries of the battery modules so as to provide electric power to the electronic apparatus.

Abstract: A power bank has a station and a plurality of battery modules. Each of the battery modules can be positioned in a corresponding slot of the station in a pluggable way and is electrically connected to a charging-discharging control circuit of the station. When a main charging port of the station is electrically connected to a power supply, the charging-discharging control circuit receives electric power from the power supply via the main charging port and uses the received electric power to charge rechargeable batteries of the battery modules. When a main discharging port of the station is electrically connected to an electronic apparatus, the charging-discharging control circuit receives electric power from the rechargeable batteries of the battery modules so as to provide electric power to the electronic apparatus.

Abstract: A power bank has a station and a plurality of battery modules. When the battery modules are stacked on the station, rechargeable batteries of the battery modules are electrically connected in parallel. When a charging port of the station is electrically connected to an external power supply, a charging-discharging control circuit of the station receives electric energy from the external power supply via the charging port and uses the received electric energy to charge the rechargeable batteries. When a discharging port of the station is electrically connected to an external electronic device, the charging-discharging control circuit transfers electric energy received from the rechargeable batteries to the external electronic device. Each of the battery modules is replaceable, and the total number of the battery modules of the power bank is adjustable.

Abstract: An audio playing system has a first channel output device, a first equalizer, and a controller. The first equalizer is configured to adjust a received first channel audio signal with a set of first parameters of frequency response and output the adjusted first channel audio signal to the first channel output device in a first mode, and to adjust the received first channel audio signal with the a of second parameters of frequency response and output the adjusted first channel audio signal to the first channel output device in a second mode. In a test mode, the controller is configured to send a set of test audio signals to the first channel output device and to adjust the set of first parameters of frequency response and the set of second parameters of frequency response based on a plurality of pieces of received first confirmation signal.

Abstract: An audio playing system has a first channel output device, a first equalizer, and a controller. The first equalizer is configured to adjust a received first channel audio signal with a set of first parameters of frequency response and output the adjusted first channel audio signal to the first channel output device in a first mode, and to adjust the received first channel audio signal with the a of second parameters of frequency response and output the adjusted first channel audio signal to the first channel output device in a second mode. In a test mode, the controller is configured to send a set of test audio signals to the first channel output device and to adjust the set of first parameters of frequency response and the set of second parameters of frequency response based on a plurality of pieces of received first confirmation signal.

Abstract: An audio playing system has a first channel output device, a first audio modulator and a controller. The first audio modulator is electrically coupled to the first channel output device and having a set of first modulation parameters, the first audio modulator configured to selectively modulate a first channel audio signal with the set of first modulation parameters and output the modulated first channel audio signal to the first channel output device. The controller is electrically coupled to the first channel output device and the first audio modulator, wherein in a test mode, the controller is configured to send a set of test audio signals to the first channel output device, to generate a set of first user parameters based on a plurality of pieces of first confirmation signal, and to adjust the set of first modulation parameters based on the set of first user parameters.

Abstract: An audio playing system has a first channel output device, a first equalizer and a controller. The first equalizer is electrically coupled to the first channel output device and having a set of first parameters of frequency response, the first equalizer configured to adjust a first channel audio signal with the set of first parameters of frequency response and output the adjusted first channel audio signal to the first channel output device. The controller is electrically coupled to the first channel output device and the first equalizer, wherein in a test mode, the controller is configured to send a set of test audio signals to the first channel output device, to generate a set of first user parameters based on a plurality of pieces of first confirmation signal, and to adjust the set of first parameters of frequency response based on the set of first user parameters.

Abstract: An audio playing system has a first channel output device, a first equalizer, a second channel output device, a second equalizer, a loudness adjusting button, and a controller. The first equalizer adjusts a first channel audio signal with a set of first parameters of frequency response and output it to the first channel output device. The second equalizer adjusts a second channel audio signal with a set of second parameters of frequency response and output it to the second channel output device. The loudness adjusting button generates a loudness instruction. The controller determines an upper limit of loudness based on the set of first parameters of frequency response and the set of second parameters of frequency response, and adjusts a loudness related to the first channel audio signal and a loudness related to the second channel audio signal based on the upper limit of loudness and the loudness instruction.

Abstract: The disclosure provides a matrix transposing circuit for outputting a transposed N×N matrix. The matrix transposing circuit includes: an input resister array with m×N array; a memory having b storage blocks; an output register array with N×m array. N, m, n, b are integer in power of 2, N can be completely divided by m and n, and N=n×m×b. The matrix is divided into multiple sub-matrixes with m×n array to form Y matrix. Each of sub-matrixes is correspondingly stored to the b storage blocks. The input resister array has a first shifting direction to receive entry data and a second shifting direction to output data to the b storage blocks. The output resister array has a first shifting direction to read data from the b storage blocks and a second shifting direction to output the transposed matrix.

Abstract: A method for prediction in image encoding and an image encoding apparatus applying the same are disclosed. The method includes steps of receiving a plurality of candidates with respect to a current prediction target of an image; calculating a distortion-based cost of a first candidate in the plurality of candidates; and for each of the other candidates, computing a data access availability and a data access requirement for calculating a distortion-based cost of a current candidate in the other candidates of the plurality of candidates; and if the data access requirement does not exceed the data access availability, calculating the distortion-based cost of the current candidate; otherwise, selecting the candidate with the minimum calculated distortion-based cost as a matched candidate for the current prediction target. Therefore, coding performance setback due to external memory data access is improved.

Abstract: The disclosure provides a matrix transposing circuit for outputting a transposed N×N matrix. The matrix transposing circuit includes: an input resister array with m×N array; a memory having b storage blocks; an output register array with N×m array. N, m, n, b are integer in power of 2, N can be completely divided by m and n, and N=n×m×b. The matrix is divided into multiple sub-matrixes with m×n array to form Y matrix. Each of sub-matrixes is correspondingly stored to the b storage blocks. The input resister array has a first shifting direction to receive entry data and a second shifting direction to output data to the b storage blocks. The output resister array has a first shifting direction to read data from the b storage blocks and a second shifting direction to output the transposed matrix.

Abstract: An electronic device assembly structure comprises two electronic devices and at least one connection module. Each electronic device includes a body and at least one USB located on the body. The connection module connects to the two electronic devices and includes an electric connection unit and a fastening unit. The electric connection unit is electrically inserted into the USBs of the two electronic devices. The fastening unit fastens the bodies of the two electronic devices together in an integrated manner.

Abstract: A method for frame memory compression divides each of a plurality of image frames in a frame memory into a plurality of blocks and quantizes a plurality of pixel values inside each block according to a predefined parameter, thereby generating a quantized block and a plurality of removed bits from the binary representation of the plurality of pixel values. A predictor is used to produce a residual block for the quantized block. A variable length encoder takes the residual block as an input and produces a coded bitstream. A packing unit is used to take the coded bitstream and the number of removed bits generated by the quantizer as inputs, so as to produce an entire codeword sequence of the block that meets a target bit rate by using a structure called group of blocks (GOB) to flexibly share available spaces of the blocks in the same GOB.

Abstract: A method for prediction in image encoding and an image encoding apparatus applying the same are disclosed. The method includes steps of receiving a plurality of candidates with respect to a current prediction target of an image; calculating a distortion-based cost of a first candidate in the plurality of candidates; and for each of the other candidates, computing a data access availability and a data access requirement for calculating a distortion-based cost of a current candidate in the other candidates of the plurality of candidates; and if the data access requirement does not exceed the data access availability, calculating the distortion-based cost of the current candidate; otherwise, selecting the candidate with the minimum calculated distortion-based cost as a matched candidate for the current prediction target. Therefore, coding performance setback due to external memory data access is improved.

Abstract: An electronic device assembly structure comprises two electronic devices and a fastening unit. Each electronic device includes a body and an electric connection module. The body has at least one opening formed thereon. The electric connection module is located in the body. The fastening unit fastens the two electronic devices together in an integrated manner. The electric connection modules of the two electronic devices form electric connection through the opening.

Abstract: An electronic device assembly structure comprises two electronic devices and at least one connection module. Each electronic device includes a body and at least one USB located on the body. The connection module connects to the two electronic devices and includes an electric connection unit and a fastening unit. The electric connection unit is electrically inserted into the USBs of the two electronic devices. The fastening unit fastens the bodies of the two electronic devices together in an integrated manner.

Abstract: A method for frame memory compression divides each of a plurality of image frames in a frame memory into a plurality of blocks for taking a block as a compression unit. It quantizes a plurality of pixel values inside the block according to a predefined parameter, thereby generating a quantized block and a plurality of removed bits from the binary representation of the plurality of pixel values. A predictor is used to produce a residual block for the quantized block. A variable length encoder takes the residual block as an input and produces a coded bitstream. A packing unit is used to take the coded bitstream and the number of removed bits generated by the quantizer as inputs, so as to produce an entire codeword sequence of the block that meets a target bit rate by using a structure called group of blocks (GOB) to flexibly share available spaces of the blocks in the same GOB.

Abstract: Disclosed are a semi-sequential Galois field GF(2n) multiplier and the method thereof. The GF(2n) multiplier comprises two ground field multipliers over GF(2m), at least a constant multiplier, and multiple GF(2m) adders. The high-order and low-order elements from a composite field GF((2m)2) for one operand of one GF(2n) multiplication are inputted in parallel into the two ground GF(2m) multipliers, respectively. The high-order and low-order elements from the composite field of another operand of the GF(2n) multiplication are sequentially inputted into the two ground GF(2m) multipliers. As such, multiple partial products are generated. The constant multiplication and additions are performed on the multiple partial products through the constant multiplier and the GF(2m) adders. This generates a high-order element and a low-order element of the composite field GF((2m)2). After mapping these two elements of GF((2m)2) back to GF(2n), the GF(2n) multiplication is done.

Abstract: A sequential Galois field (GF) multiplication architecture based on Mastrovito's multiplication and composite field has a two-tier architecture for performing GF(2k) multiplication. The tier one prepares related data of an operand A at one time, and proceeds another operand B by sequentially inputting m n-bit data, where k=m×n. The tier two sequentially receives the m inputted n-bit data, and directly performs GF((2n)m) multiplication with m n-bit multipliers. Before the data processing of the first architecture, operands A and B are transformed from a field GF(2k) into a composite field GF((2n)m) While a multiplication result from the tier two is transformed from the composite field GF((2n)m) back to the field GF(2k) for completing the GF(2k) multiplication.