Patents by Inventor Chih-Hsuan Lin
Chih-Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210357251Abstract: A test path coordination method includes obtaining information of a number of products to be tested, obtaining information of each test device, and planning a test path of each product according to a preset rule according to the information of the products and the information of each test device. The information of the products includes the number of the products, test items of each product, and test devices required for testing the test items. The information of each test device includes whether the test device is currently testing a product and test information of the product currently being tested. The test information of the product includes a length of time the product has been tested and a test result. The test path includes a test sequence of each product and a test sequence of the test items of each product.Type: ApplicationFiled: June 11, 2020Publication date: November 18, 2021Inventors: CHIH-HSUAN LIN, SHANG-YI LIN
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Publication number: 20210328425Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.Type: ApplicationFiled: April 21, 2020Publication date: October 21, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Yeh-Ning JOU, Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Hwa-Chyi CHIOU
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Patent number: 11043486Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.Type: GrantFiled: November 7, 2018Date of Patent: June 22, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Hsuan Lin, Shao-Chang Huang, Jia-Rong Yeh, Yeh-Ning Jou, Hwa-Chyi Chiou
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Patent number: 11022878Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.Type: GrantFiled: October 18, 2019Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Co.. Ltd.Inventors: Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Chih-Hsuan Lin
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Publication number: 20210125943Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: ApplicationFiled: October 23, 2019Publication date: April 29, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Yu-Kai WANG, Karuna NIDHI, Hwa-Chyi CHIOU
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Publication number: 20210075215Abstract: An operating circuit is provided. A first N-type transistor determines whether to turn the path between a core circuit and a ground terminal on or off according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific circuit according to the first detection signal.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang Huang, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Chun-Chih Chen, Kai-Chieh Hsu, Chih-Hsuan Lin, Yu-Kai Wang
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Patent number: 10879109Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.Type: GrantFiled: April 20, 2020Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xi-Zong Chen, Chih-Hsuan Lin, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu
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Patent number: 10867989Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.Type: GrantFiled: July 30, 2018Date of Patent: December 15, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Hsuan Lin, Shao-Chang Huang, Chun-Chih Chen, Hwa-Chyi Chiou
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Patent number: 10784252Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.Type: GrantFiled: September 20, 2018Date of Patent: September 22, 2020Assignee: Vanguard International Semiconductor CorporationInventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
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Publication number: 20200251382Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xi-Zong CHEN, Chih-Hsuan LIN, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU
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Publication number: 20200144246Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.Type: ApplicationFiled: November 7, 2018Publication date: May 7, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Hsuan LIN, Shao-Chang HUANG, Jia-Rong YEH, Yeh-Ning JOU, Hwa-Chyi CHIOU
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Patent number: 10643987Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.Type: GrantFiled: June 25, 2018Date of Patent: May 5, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin
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Patent number: 10629480Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a first recess and a second recess in the first layer. The first recess is narrower than the second recess. The method includes forming a first covering layer in the first recess and the second recess. The first covering layer in the first recess is thinner than the first covering layer in the second recess. The method includes removing the first covering layer in the first recess and the first covering layer covering the first bottom surface to form a first opening in the first covering layer in the second recess. The method includes removing the first portion and the second portion through the first recess and the first opening.Type: GrantFiled: August 17, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xi-Zong Chen, Chih-Hsuan Lin, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu
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Publication number: 20200098740Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.Type: ApplicationFiled: September 20, 2018Publication date: March 26, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Shao-Chang HUANG, Li-Fan CHEN, Chih-Hsuan LIN, Yu-Kai WANG, Hung-Wei CHEN, Ching-Wen WANG, Ting-You LIN, Chun-Chih CHEN
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Publication number: 20200050103Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Chih-Hsuan Lin
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Publication number: 20200036376Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.Type: ApplicationFiled: July 30, 2018Publication date: January 30, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Hsuan LIN, Shao-Chang HUANG, Chun-Chih CHEN, Hwa-Chyi CHIOU
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Publication number: 20190393208Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN
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Patent number: 10517183Abstract: A hold and release device of reduced size allowing the sliding of a server chassis relative to a rack includes a mounting assembly mounted to the server chassis. A fixing member is rotatably coupled to the mounting assembly and comprises a first protrusion to fasten the server chassis to the rack. A latching button is configured to latch the fixing member to the mounting assembly. A guiding member is connected to a button stage receives the latching button and has a sliding tunnel, and a handle slidably coupled to the guiding member is located in the sliding tunnel.Type: GrantFiled: January 29, 2019Date of Patent: December 24, 2019Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.Inventors: Ying-Jui Huang, Chih-Hsuan Lin
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Patent number: 10495970Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.Type: GrantFiled: August 10, 2018Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Chih-Hsuan Lin
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Publication number: 20190164816Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a second layer. The method includes forming a first recess and a second recess in the first layer. The first recess is narrower than the second recess. The method includes forming a first covering layer in the first recess and the second recess. The first covering layer in the first recess is thinner than the first covering layer in the second recess. The method includes removing the first covering layer in the first recess and the first covering layer covering the first bottom surface to form a first opening in the first covering layer in the second recess. The method includes removing the first portion and the second portion through the first recess and the first opening.Type: ApplicationFiled: August 17, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xi-Zong CHEN, Chih-Hsuan LIN, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU