Patents by Inventor Chih-Hsun Lin
Chih-Hsun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11986869Abstract: A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support. A cleaning fluid inlet line is attached to a first open-ended tubular quartz projection extending from an outer main surface of the semiconductor device manufacturing tool component. A cleaning fluid is applied to the semiconductor device manufacturing tool component by introducing the cleaning fluid through the cleaning fluid inlet line and the tubular quartz projection.Type: GrantFiled: June 6, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi Chen Ho, Chih Ping Liao, Ker-hsun Liao, Chi-Hsun Lin
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Publication number: 20240162308Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.Type: ApplicationFiled: February 9, 2023Publication date: May 16, 2024Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
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Patent number: 11982936Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.Type: GrantFiled: June 30, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Ping-Hsun Lin, Yen-Cheng Ho, Chih-Cheng Lin, Chia-Jen Chen
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Publication number: 20240094625Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Chih-Cheng LIN, Chia-Jen CHEN
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Publication number: 20240094615Abstract: An illumination system including a first light-emitting unit, a first reflector, a second light-emitting unit, and a second reflector is provided. The first light-emitting unit is configured to emit a first light beam, and the first reflector is configured to reflect the first light beam toward a first direction. The second light-emitting unit is configured to emit a second light beam, and the second reflector is configured to reflect the second light beam toward the first direction. The first reflector and the second reflector are arranged in a second direction. For a view seeing along the second direction, the first reflector and the second reflector form a cross shape. The second direction is perpendicular to the first direction. A projection apparatus is also provided.Type: ApplicationFiled: May 17, 2023Publication date: March 21, 2024Applicant: Qisda CorporationInventors: Chih-Shiung Chien, Ming-Kuen Lin, Tsung-Hsun Wu
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Patent number: 11929767Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.Type: GrantFiled: August 16, 2022Date of Patent: March 12, 2024Assignee: MEDIATEK INC.Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
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Publication number: 20240077188Abstract: A light source module includes a first light source and a second light source. The first light source is configured for emitting a first light having a first wavelength, and the first light includes a first part and a second part. The second light source is configured for emitting a second light having a second wavelength. The second light source includes a first wavelength conversion layer, and the first wavelength conversion layer is configured for converting the first light into the second light. One of the first part and the second part is incident to the first wavelength conversion layer, and the other of the first part and the second part is not incident to the first wavelength conversion layer.Type: ApplicationFiled: August 22, 2023Publication date: March 7, 2024Applicant: Qisda CorporationInventors: Chih-Shiung CHIEN, Ming-Kuen LIN, Tsung-Hsun WU, Yi-Ling LO
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Publication number: 20230018182Abstract: The present invention provides a simulated inflatable wheel including a rim, a filler tire mounted on the rim, and a tire casing covering the filler tire and having a rolling portion in rolling contact with the external environment and an abutting portion extending from two sides of the rolling portion. The abutting portion is located between the rim and the filler tire. The abutting portion abuts against the rim and the filler tire respectively. A recessed portion is formed on at least one position of an outer surface of the filler tire. The present invention utilizes the recessed portion of the filler tire to generate space between the filler tire and the rim (or the tire casing), for providing a buffer when the filler tire is deformed and improving elasticity of the filler tire. The present invention further provides a stroller including the simulated inflatable wheel.Type: ApplicationFiled: December 16, 2020Publication date: January 19, 2023Applicant: WONDERLAND SWITZERLAND AGInventors: Chih-Hsun LIN, Jian Yong TANG
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Publication number: 20220390628Abstract: The invention is related to particle induced radiography system, comprising a particle radiation source device, implant module, external detector device, central module and other controls, in which the implant module comprises active and/or passive components in tandem with the readout electronics and communication chosen to measure the beam properties and to generate and detect secondary gamma photons from the nuclear interactions, the external detector device provides a position sensitive gamma detector with a high detection efficiency, good spatial resolution and a relatively large field of view necessary for particle treatments useful in monitoring both the implanted device and the patient anatomical areas under treatment, and the external detector device can also be used to perform 3D spectral imaging on any material samples using proton beam as a probe.Type: ApplicationFiled: June 8, 2022Publication date: December 8, 2022Applicants: Academia Sinica, National Central UniversityInventors: Mythra Varun Nemallapudi, Chih-Hsun Lin, Shih-Chang Lee, Augustine Ei-fong Chen
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Publication number: 20220359395Abstract: A method includes following steps. An image of a wafer is captured. A first contact region in the captured image at which the first conductive contact is rendered is identified. A second contact region in the captured image at which the second conductive contact is rendered is identified. The second conductive contact is determined as not shorted to the first conductive contact, in response to the identified second contact region in the captured image is darker than the identified first contact region in the captured image.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Hsung HO, Chia-Yi TSENG, Chih-Hsun LIN, Kun-Tsang CHUANG, Yung-Lung HSU
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Patent number: 11430733Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.Type: GrantFiled: October 23, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Kun-Tsang Chuang, Yung-Lung Hsu
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Patent number: 11257719Abstract: Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer.Type: GrantFiled: June 1, 2020Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Wei Su, Chun Yu Huang, Chih-Hsun Lin, Ping-Pang Hsieh
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Publication number: 20210043566Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Hsung HO, Chia-Yi TSENG, Chih-Hsun LIN, Kun-Tsang CHUANG, Yung-Lung HSU
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Patent number: 10818595Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first feature has a first electrical resistance, the second feature has a second electrical resistance, and the first electrical resistance is different form the second electrical resistance; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.Type: GrantFiled: April 13, 2017Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Kun-Tsang Chuang, Yung-Lung Hsu
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Patent number: 10809469Abstract: A method and a system for active alignment of a light source assembly along three dimensions in an optical bench plane are provided. The light source assembly, preferably a laser diode on its sub-mount, is actively aligned in three dimensions, longitudinal, transection and vertical along the optical bench. The light source assembly is attached on edge of the optical bench, via adhesion processes, such as solder welding. Optical components such as collimator lens, isolator, etc are first passively aligned on the optical bench using alignment marks and epoxy slots provided on the surface of the optical bench. Then, laser diode, mounted on a laser diode sub-mount, is aligned in X and Z direction. Thereafter, the light source assembly is pushed towards the edge of the optical bench and attached with the edge via a solder joint. Also, a compensator can be actively aligned until the optimum light intensity achieved.Type: GrantFiled: April 2, 2019Date of Patent: October 20, 2020Assignee: Cloud Light Technology LimitedInventors: Vincent Wai Hung, Vivian Wei Ma, Wing Keung Mark Mak, Chih Hsun Lin
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Publication number: 20200319415Abstract: A method and a system for active alignment of a light source assembly along three dimensions in an optical bench plane are provided. The light source assembly, preferably a laser diode on its sub-mount, is actively aligned in three dimensions, longitudinal, transection and vertical along the optical bench. The light source assembly is attached on edge of the optical bench, via adhesion processes, such as solder welding. Optical components such as collimator lens, isolator, etc are first passively aligned on the optical bench using alignment marks and epoxy slots provided on the surface of the optical bench. Then, laser diode, mounted on a laser diode sub-mount, is aligned in X and Z direction. Thereafter, the light source assembly is pushed towards the edge of the optical bench and attached with the edge via a solder joint. Also, a compensator can be actively aligned until the optimum light intensity achieved.Type: ApplicationFiled: April 2, 2019Publication date: October 8, 2020Inventors: Vincent Wai Hung, Vivian Wei Ma, Wing Keung Mark Mak, Chih Hsun Lin
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Publication number: 20200294862Abstract: Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer.Type: ApplicationFiled: June 1, 2020Publication date: September 17, 2020Inventors: Kuan-Wei Su, Chun Yu Huang, Chih-Hsun Lin, Ping-Pang Hsieh
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Publication number: 20200238645Abstract: A process for making a wheel assembly for a lightweight vehicle includes the steps of: (a) providing a wheel which includes a rim having a recessed outer surface, (b) disposing a foam tire core on the wheel such that an inner annular surface of the foam tire core is in abutment with the recessed outer surface of the rim, (c) applying an adhesive agent on at least one of an inner surface of a rubber casing and an outer annular surface of the foam tire core, and (d) wrapping the rubber casing on the foam tire core such that the inner surface of the rubber casing is brought into press engagement with the outer annular surface of the foam tire core.Type: ApplicationFiled: April 24, 2019Publication date: July 30, 2020Inventor: Chih-Hsun LIN
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Patent number: 10699960Abstract: Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.Type: GrantFiled: August 30, 2018Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Wei Su, Chun Yu Huang, Chih-Hsun Lin, Ping-Pang Hsieh
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Patent number: 10672777Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.Type: GrantFiled: February 18, 2019Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Kun-Tsang Chuang, Chiang-Ming Chuang, Chia-Yi Tseng