Patents by Inventor Chih-Hung Chiang

Chih-Hung Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984361
    Abstract: A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lo-Heng Chang, Chih-Hao Wang, Kuo-Cheng Chiang, Jung-Hung Chang, Pei-Hsun Wang
  • Patent number: 11980694
    Abstract: A sterilization apparatus for a portable electronic device including a cabinet and a carrier is provided. The carrier includes a base slidably disposed on the cabinet, multiple first positioning elements and multiple second positioning elements disposed in parallel on the base, multiple sterilization light sources corresponding to the second positioning elements and multiple pressure sensors disposed in parallel in the base. The base is configured to carry at least one portable electronic device. One second positioning element is disposed between any two adjacent first positioning elements, and any first positioning element and any second positioning element adjacent to each other are separated by a positioning space. The pressure sensors are respectively located in the positioning spaces. One sterilization light source is disposed between any two adjacent pressure sensors, and the pressure sensors are configured to sense a pressure from the portable electronic device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yi-Hung Chen, Chih-Wen Chiang, Yun-Tung Pai, Yen-Hua Hsiao, Yao-Kuang Su, Yi-Hsuan Lin, Han-Sheng Siao
  • Publication number: 20240153958
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 9, 2024
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11967594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240079263
    Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.
    Type: Application
    Filed: February 22, 2023
    Publication date: March 7, 2024
    Inventors: Kai-Hung HSIAO, Chi-Chung JEN, Yu-Chun SHEN, Yuan-Cheng KUO, Chih-Hsiung HUANG, Wen-Chih CHIANG
  • Publication number: 20240077914
    Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chih-Han Chang, Tsung-Ju Chiang, Chi-Hung Lin, Yen-Ting Liu
  • Publication number: 20230036669
    Abstract: A method for assembling a shoe upper and a bottom unit includes digitally determining a bite line on the shoe upper. The method further includes storing a set of data representing the bite line in a computing device. The method also includes utilizing the set of data to automatically indicate the location of an actual physical bite line on the shoe upper.
    Type: Application
    Filed: October 6, 2022
    Publication date: February 2, 2023
    Inventors: Chiung Li Chang, Yu-Sung Chen, Chih-Hung Chiang
  • Patent number: 11490693
    Abstract: A method for assembling a shoe upper and a bottom unit includes digitally determining a bite line on the shoe upper. The method further includes storing a set of data representing the bite line in a computing device. The method also includes utilizing the set of data to automatically indicate the location of an actual physical bite line on the shoe upper.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 8, 2022
    Assignee: NIKE, Inc.
    Inventors: Chiung Li Chang, Yu-Sung Chen, Chih-Hung Chiang
  • Publication number: 20210090735
    Abstract: The present invention provides a method fir emergency treatment by artificial intelligence. An artificial neural network is used as the artificial intelligence. Firstly the artificial neural network is trained to make injury classification, inspection list and medical material scheduling correctly. For a patient entering the hospital, the artificial neural network that has been successfully trained is used to accept a plurality of word vectors and various physiological information of the patient to generate an injury classification. The artificial neural network then determines whether the patient has to perform various inspection items respectively with the highest level of the injury classification. The artificial neural network then determines whether the patient needs the various medical materials with the highest level of the injury classification.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Ren Shi SHYU, Lit Min NG, Shaw Hwa HWANG, Yu CHIANG, Bing Chih YAO, Cheng Yu YEH, Chih Hung CHIANG, Kun Ching CHANG, You Shuo CHEN, Yao Hsing CHUNG, Li Te SHEN, Chi Jung HUANG, Shun Chieh CHANG, Ning Yun KU
  • Publication number: 20190365054
    Abstract: A method for assembling a shoe upper and a bottom unit includes digitally determining a bite line on the shoe upper. The method further includes storing a set of data representing the bite line in a computing device. The method also includes utilizing the set of data to automatically indicate the location of an actual physical bite line on the shoe upper.
    Type: Application
    Filed: May 28, 2019
    Publication date: December 5, 2019
    Inventors: Chiung Li CHANG, Yu-Sung CHEN, Chih-Hung CHIANG
  • Patent number: 9965365
    Abstract: A power supply failover system/method providing uninterruptable power to protected load devices (PLD) is disclosed. The system includes a failover switch controller (FSC) with inputs from an AC I/V monitor (AIV), AC cycle counter (ACC), failover switch timer (FST), and overcurrent protection timer (OPT). The FSC utilizes these inputs to control failsafe switching of a bypass phase switch (BPS) and AC phase switch (ACS) to the PLD when power from the APS is determined to be good by the AIV. When power from the APS is determined to be compromised by the AIV, the FPS disables the ACS/BPS and enables a DC switch (DCS) and battery isolation switch (BIS) to connect a DC source to the PLD after a time period determined by the FST. APS/DCS overcurrent protection is limited by OPT intervals allowing a smooth transition between the APS to DCS during power failover/failback.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: May 8, 2018
    Assignee: LITE-ON, INC.
    Inventors: Victor K. J. Lee, Yung Hsiang Liu, Wei Kang Liang, Yu Kai Wang, Chih Hung Chiang
  • Publication number: 20160154716
    Abstract: A power supply failover system/method providing uninterruptable power to protected load devices (PLD) is disclosed. The system includes a failover switch controller (FSC) with inputs from an AC I/V monitor (AIV), AC cycle counter (ACC), failover switch timer (FST), and overcurrent protection timer (OPT). The FSC utilizes these inputs to control failsafe switching of a bypass phase switch (BPS) and AC phase switch (ACS) to the PLD when power from the APS is determined to be good by the AIV. When power from the APS is determined to be compromised by the AIV, the FPS disables the ACS/BPS and enables a DC switch (DCS) and battery isolation switch (BIS) to connect a DC source to the PLD after a time period determined by the FST. APS/DCS overcurrent protection is limited by OPT intervals allowing a smooth transition between the APS to DCS during power failover/failback.
    Type: Application
    Filed: January 22, 2016
    Publication date: June 2, 2016
    Applicant: Lite-On, Inc.
    Inventors: Victor K. J. LEE, Yung Hsiang LIU, Wei Kang LIANG, Yu Kai WANG, Chih Hung CHIANG
  • Publication number: 20160063947
    Abstract: A system and method for interacting multi-screen in a car are presented. A memory of a main device is configured to form a main frame buffer corresponding to the main device and to form at least one secondary frame buffer corresponding to the at least one secondary device. The memory is further configured to form a frequently executed icon frame buffer corresponding to a frequently executed icon to store a user interface image when the controller is performing function of the frequently executed icon. A user interface is used to select a touch screen icon and frequently executed icon for the touch screen to be directed to a corresponding frame buffer and immediately display and control images in the corresponding touch screen to improve the interaction between touch screens.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 3, 2016
    Inventors: Wen-Jing Lin, Hsin-Chih Hung, Chih-Hung Chiang, Jen-Wei Lou, Wen-Chun Kang, Ping Liang
  • Patent number: 8125795
    Abstract: The present invention relates to a surface-mount connector for electrically interconnecting a first circuit board and a second circuit board. The surface-mount connector includes a first end part and a second end part. The first end part is bonded onto the first circuit board. The second end part has a sidewall and a receptacle defined within the sidewall for receiving a solder bump therein. The solder bump is partially protruded from the sidewall and bonded onto the second circuit board such that the first circuit board and the second circuit board are electrically connected to each other.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 28, 2012
    Assignee: Delta Electronics, Inc.
    Inventors: Chih-Hung Chiang, Kai-Hung Huang
  • Publication number: 20100268691
    Abstract: The invention relates to a framework system and methods for connecting a plurality of tools. The system comprises a plug-in mechanism configured to dynamically load the plurality of tools, a data pool having storage space configured to store data sets associated with the plurality of tools, a linking mechanism configured to establish communications links between the loaded plurality of tools to enable coordinated operation of the loaded plurality of tools, a session component configured to record the process history of the operations of the loaded plurality of tool and the system states corresponding to the process history of the operations and an annotation module configured to associate user-provided data corresponding to one or more of the stored data sets.
    Type: Application
    Filed: June 8, 2010
    Publication date: October 21, 2010
    Applicant: UNIVERSITY OF MASSACHUSETTS
    Inventors: Georges Grinstein, Alexander Gee, Urska Cvek, Howard Goodell, Hongli Li, Min Yu, Jianping Zhou, Vivek Gupta, Mary Beth Smrtic, Christine Lawrence, Chih-Hung Chiang
  • Patent number: 7734607
    Abstract: The invention relates to a framework system and methods for connecting a plurality of tools. The system comprises a plug-in mechanism configured to dynamically load the plurality of tools, a data pool having storage space configured to store data sets associated with the plurality of tools, a linking mechanism configured to establish communications links between the loaded plurality of tools to enable coordinated operation of the loaded plurality of tools, a session component configured to record the process history of the operations of the loaded plurality of tool and the system states corresponding to the process history of the operations and an annotation module configured to associate user-provided data corresponding to one or more of the stored data sets.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: June 8, 2010
    Assignee: University of Massachusetts
    Inventors: Georges Grinstein, Alexander Gee, Urska Cvek, Howard Goodell, Hongli Li, Min Yu, Jianping Zhou, Vivek Gupta, Mary Beth Smrtic, Christine Lawrence, Chih-Hung Chiang
  • Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee