Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.

Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.

Abstract: An operation method of a semiconductor removing apparatus includes moving a semiconductor structure to a stage, wherein the semiconductor structure includes a lower substrate, a cap, and a micro electro mechanical system (MEMS) structure between the lower substrate and the cap, and the cap has a diced portion; pulling, by a clamp assembly, a tape of a tape roll from a first side of the stage to a second side of the stage opposite to the first side, such that the tape is attached to the cap of the semiconductor structure; and pulling, by the clamp assembly, the tape of the tape roll from the second side of the stage back to the first side of the stage, such that the diced portion of the cap separates from the semiconductor structure.

Abstract: An operation method of a semiconductor removing apparatus includes moving a semiconductor structure to a stage, wherein the semiconductor structure includes a lower substrate, a cap, and a micro electro mechanical system (MEMS) structure between the lower substrate and the cap, and the cap has a diced portion; pulling, by a clamp assembly, a tape of a tape roll from a first side of the stage to a second side of the stage opposite to the first side, such that the tape is attached to the cap of the semiconductor structure; and pulling, by the clamp assembly, the tape of the tape roll from the second side of the stage back to the first side of the stage, such that the diced portion of the cap separates from the semiconductor structure.

Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.

Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.