Patents by Inventor Chih-Hung SUN
Chih-Hung SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369462Abstract: In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.Type: ApplicationFiled: May 16, 2022Publication date: November 16, 2023Inventors: Chih-Hung SUN, Po-Hsien CHENG, Zhen-Cheng WU, Chi-On CHUI
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Publication number: 20230369428Abstract: Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.Type: ApplicationFiled: July 22, 2022Publication date: November 16, 2023Inventors: Chih-Hung Sun, Wen-Kai Lin, Che-Hao Chang, Zhen-Cheng Wu, Chi On Chui
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Patent number: 10978341Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: GrantFiled: December 5, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Publication number: 20200111705Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Patent number: 10510593Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: GrantFiled: January 12, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Publication number: 20180151425Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: ApplicationFiled: January 12, 2018Publication date: May 31, 2018Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Patent number: 9881834Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.Type: GrantFiled: March 17, 2017Date of Patent: January 30, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
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Patent number: 9373581Abstract: Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.Type: GrantFiled: February 5, 2015Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng Shih, Joung-Wei Liou, Chih-Hung Sun, Chia-Cheng Chou, Kuang-Yuan Hsu
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Patent number: 9269614Abstract: A method of forming a semiconductor device comprises forming a first etch stop layer over a substrate. The method also comprises forming a low-k dielectric layer comprising carbon over the first etch stop layer. The method further comprises forming an opening in the low-k dielectric layer. The method additionally comprises filling the opening with a conductive layer. The method also comprises performing a remote plasma treatment on the low-k dielectric layer and the conductive layer. The method further comprises forming a second etch stop layer over the treated conductive layer and the treated low-k dielectric layer.Type: GrantFiled: February 26, 2015Date of Patent: February 23, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng Shih, Hui-Chun Yang, Chih-Hung Sun, Joung-Wei Liou
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Patent number: 9236294Abstract: Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.Type: GrantFiled: January 13, 2014Date of Patent: January 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Cheng Chou, Chung-Chi Ko, Po-Cheng Shih, Chih-Hung Sun, Kuang-Yuan Hsu, Joung-Wei Liou, Tze-Liang Lee
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Publication number: 20150200133Abstract: Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.Type: ApplicationFiled: January 13, 2014Publication date: July 16, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng CHOU, Chung-Chi KO, Po-Cheng SHIH, Chih-Hung SUN, Kuang-Yuan HSU, Joung-Wei LIOU, Tze-Liang LEE
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Publication number: 20150170960Abstract: A method of forming a semiconductor device comprises forming a first etch stop layer over a substrate. The method also comprises forming a low-k dielectric layer comprising carbon over the first etch stop layer. The method further comprises forming an opening in the low-k dielectric layer. The method additionally comprises filling the opening with a conductive layer. The method also comprises performing a remote plasma treatment on the low-k dielectric layer and the conductive layer. The method further comprises forming a second etch stop layer over the treated conductive layer and the treated low-k dielectric layer.Type: ApplicationFiled: February 26, 2015Publication date: June 18, 2015Inventors: Po-Cheng SHIH, Hui-Chun YANG, Chih-Hung SUN, Joung-Wei LIOU
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Publication number: 20150155234Abstract: Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Inventors: Po-Cheng Shih, Joung-Wei Liou, Chih-Hung Sun, Chia-Cheng Chou, Kuang-Yuan Hsu
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Patent number: 8994178Abstract: A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom portion. A difference of C content in the top portion and the bottom portion is less than 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %.Type: GrantFiled: May 18, 2012Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng Shih, Hui-Chun Yang, Chih-Hung Sun, Joung-Wei Liou
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Patent number: 8993442Abstract: Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %.Type: GrantFiled: August 23, 2013Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng Shih, Joung-Wei Liou, Chih-Hung Sun, Chia Cheng Chou, Kuang-Yuan Hsu
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Publication number: 20150056802Abstract: Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng Shih, Joung-Wei Liou, Chih-Hung Sun, Chia Cheng Chou, Kuang-Yuan Hsu
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Publication number: 20130256888Abstract: A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom potion. A difference of C content in the top portion and the bottom potion is less than 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %.Type: ApplicationFiled: May 18, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng SHIH, Hui-Chun YANG, Chih-Hung SUN, Joung-Wei LIOU
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Patent number: D1021220Type: GrantFiled: July 15, 2021Date of Patent: April 2, 2024Assignee: Radiant Opto-Electronics CorporationInventors: Cheng-Ang Chang, Guo-Hao Huang, Chun-Yi Sun, Chih-Hung Ju, Pin-Tsung Wang