Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

Abstract: A multi slide doors device comprises a frame, a power module, a guide pulley module and a plurality of door panels. The first door panel is operated by the power module to move upward or downward. Simultaneously, the second door panel also moves in the same direction with a different moving distance by the transmission of the pulleys in the pulley module. The moving distance of the second door panel is larger than that of the first door panel. In this way, the plurality of door panels can be opened or closed quickly so that the defect of spending long time in opening or closing due to in-sequence moving of door panels and of inconvenient maintenance due to complexity in designing of convention technology can be improved.

Abstract: A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

Abstract: A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

Abstract: A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

Abstract: A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.

Abstract: A driving circuit applied to a display panel includes a driving unit for generating a plurality of driving signals to drive a plurality of pixels in the display panel, and a plurality of multiplexers coupled to the driving unit and the plurality of pixels. Each multiplexer of the plurality of multiplexers is utilized for sequentially transmitting a plurality of driving signals to a plurality of sub-pixels of a corresponding pixel, where two adjacent pixels utilize different driving sequences of the sub-pixels to drive their sub-pixels.

Abstract: A method for fabricating thin film transistors is disclosed. An amorphous silicon film is formed on a substrated and selectively irradiated with a laser beam for lateral growth to form a plurality of polysilicon regions. The whole surface of the substrate is then oxidized and irradiated with exicer laser annealing.

Abstract: A method of fabricating a polysilicon layer is provided. A substrate having a front surface and a back surface is provided. A buffer layer, an amorphous layer and a cap layer are sequentially formed on the front surface of the substrate. The cap layer is patterned to form a patterned cap layer exposing a portion of the amorphous layer, wherein the exposed portion of the amorphous layer is a crystallization initial region. A metallic catalytic layer is formed on the patterned cap layer, wherein the metallic catalytic layer contacts with the crystallization initial region of the amorphous layer. A laser annealing process is performed through the back surface of the substrate so that the amorphous layer is crystallized and transformed into a polysilicon layer from the crystallization initial region.

Abstract: A thin film transistor having a substrate, a gate insulating layer, a double-gate structure, a first lightly doped region, and a second lightly doped region. The substrate has a source region and a drain region disposed on its opposite sides, a heavily doped region between source region and drain region, a first channel region between heavily doped region and source region and a second channel region between heavily doped region and drain region. The gate insulating layer covers the substrate. The double-gate structure has a first gate and a second gate disposed on gate insulating layer above the first and the second channel region, respectively. The first lightly doped region is disposed between second channel region and heavily doped region and the second lightly doped region between second channel region and drain region. The length of second lightly doped region is greater than that of first lightly doped region.