Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A flower receptacle with a water lamp handicraft, including: a water lamp ornament, where the water lamp ornament includes a water lamp body and a top ornament, and the water lamp body is a hollow and a light-transmissive three-dimensional structure and holds a thick liquid inside, and the top ornament is mounted on the water lamp body; a fixing member, connected to the top ornament, and forming a customized three-dimensional model with the top ornament; and a flower receptacle base, having a tapered structure, mounted on the fixing member, and used for arranging flowers. In the present application, the fixing member and the top ornament are combined, to enable the fixing member and the water lamp ornament to form a unique three-dimensional model.

Abstract: The present invention discloses a power converter controller having a short-circuit protection threshold voltage no higher than an over-current protection threshold voltage so that any abnormal voltage or current stress on semiconductor components can be timely sensed via a current sense pin in the event of a short-circuit fault, effectively preventing semiconductor components from being damaged.

Abstract: The present invention discloses a power converter controller having a short-circuit protection threshold voltage no higher than an over-current protection threshold voltage so that any abnormal voltage or current stress on semiconductor components can be timely sensed via a current sense pin in the event of a short-circuit fault, effectively preventing semiconductor components from being damaged.

Abstract: The present invention discloses a power converter controller with short-circuit protection employing a short-circuit protection increasing slope threshold no higher than an over-current protection increasing slope threshold to detect a short-circuit abnormality in advance through a current sensing pin while any semiconductor component suffering from abnormal voltage or over-current, thereby preventing the semiconductor components from damage.

Abstract: Disclosed is a method of dynamical adjustment for a power supply. The method takes aim at lowering the minimum bulk capacitor voltage to the maximum extent through increasing the switching frequency or the OCP (Over-Current Protection) trip point during the holdup time so that the holdup time can get prolonged or the bulk capacitor can get downsized provided that all other parameters remain unchanged. In general, the proposed method is applicable to a wide variety of power converters.

Abstract: Disclosed is an Auxiliary-Free High-Side Driven Secondary-Side Regulated (AF-HSD-SSR) flyback converter, which includes an AC-to-DC rectification unit, an input capacitor, a switching unit, a current-sensing resistor, an Auxiliary-Free (AF) flyback transformer, an output rectifier, an output capacitor, a PWM controller, and a SSR unit. The AF flyback transformer includes a primary winding and a secondary winding, where the primary winding is split into two halves. The switching unit is placed at the high side of the primary winding, and the PWM controller in collocation with the SSR unit drives the switching unit in response to all the required voltage and current sense signals to keep voltage conversion and power delivery safe and efficient within the specifications. The first half of the primary winding can provide the PWM controller with a continuous and steady working voltage supply after startup, thus eliminating the need for the auxiliary winding.

Abstract: A power supply and a method of power supplying for converting an external alternating power into an output power with appropriate voltage and power are disclosed. The power supply includes an input charging unit, an input filtering unit, a regulating unit, a transformer, a controller, an output unit, an output capacitor, a switching unit and a feedback unit. The regulating unit is connected to the input filtering unit and comprises a regulating capacitor and a regulator connected in series. The regulator is controlled by the controller to perform one of the working modes including initial open circuit, power on conduction, short circuit normal operation and over-voltage open circuit protection. Therefore, the present invention overcomes the problem of inrush current upon powering on, and particularly, the controller performs digital operation with flexibility to meet actual requirements by updating appropriate firmware of software program.

Abstract: A power supply and a method of power supplying for converting an external alternating power into an output power with appropriate voltage and power are disclosed. The power supply includes an input charging unit, an input filtering unit, a regulating unit, a transformer, a controller, an output unit, an output capacitor, a switching unit and a feedback unit. The regulating unit is connected to the input filtering unit and comprises a regulating capacitor and a regulator connected in series. The regulator is controlled by the controller to perform one of the working modes including initial open circuit, power on conduction, short circuit normal operation and over-voltage open circuit protection. Therefore, the present invention overcomes the problem of inrush current upon powering on, and particularly, the controller performs digital operation with flexibility to meet actual requirements by updating appropriate firmware of software program.

Abstract: An apparatus for controlling a display having a backlight module provided with a first set of units and a display panel provided with a second set of units is provided. In one embodiment, the apparatus comprises a reference value generator, a control value generator, and a compensation circuit. The reference value generator generates a reference value representative of a portion of pixels contained in an input image associated with one of the second set of units. The control value generator generates a control value to control one of the first set of units in view of the reference value. The compensation circuit adjusts the portion of pixels contained in the input image in view of the control value. The one of the first units is associated with the one of the second units.

Abstract: An image adjusting method for extending vertical blanking intervals of an image signal is provided. Using the image adjusting method, an adjusted image signal is synchronized with an image signal before the adjustment to prevent image delay. The image adjusting method comprises providing a first image signal having a first data enable signal, wherein the first data enable signal has a first data enable duration; and generating a second data enable signal having a second data enable duration. The first and second data enable durations correspond to a same image frame of an image signal, and the second data enable duration substantially overlaps the first data enable duration.

Abstract: An ac-powered LED light engine coupled between a rectifier and a plurality of extrinsic LED sub-arrays is provided. The ac-powered LED light engine comprises a plurality of normally closed bypass switches, a normally closed current regulator, and a plurality of switch controllers. Each of the normally closed bypass switches is connected in parallel with a corresponding LED sub-array except for the topmost or the bottommost LED sub-array and shuttles between three switch states: ON, REGULATION, and OFF. The normally closed current regulator is coupled to the normally closed bypass switches and used to regulate the highest LED current level near the peak of an extrinsic mains voltage. Each of the switch controllers is coupled to a corresponding bypass switch as a feedback network and takes control of the three switch states according to a corresponding current sense signal.