Patents by Inventor Chih-Lung Hung
Chih-Lung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11067745Abstract: A display assembly includes at least two display devices and two image compensating elements at a juxtaposition of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. Each image compensating element includes a first part and a second part independent from each other, the first part is closer to the border area than the second part. Each of the first part and the second part includes a plurality of light guiding channels extending along a direction from a light-incident surface toward a light-emitting surface.Type: GrantFiled: July 20, 2020Date of Patent: July 20, 2021Assignee: SEAMLESS TECHNOLOGY INC.Inventors: I-Wei Wu, Hsueh-Min Yin, Chih-Lung Hung
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Patent number: 11067740Abstract: A display assembly includes at least two display devices and two image compensating elements at a junction of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. An optical axis direction of each of the image compensating elements is relatively toward above the juxtaposition of the adjacent two display devices. A light guiding sheet is positioned on the light-emitting surface of each of the image compensating elements; an optical axis direction of the light guiding sheet is perpendicular to the front surface.Type: GrantFiled: November 15, 2019Date of Patent: July 20, 2021Assignee: SEAMLESS TECHNOLOGY INC.Inventors: I-Wei Wu, Chih-Lung Hung
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Patent number: 10958093Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.Type: GrantFiled: March 18, 2020Date of Patent: March 23, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tau-Jing Yang, Kuo-Feng Huang, Chih Lung Hung
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Patent number: 10725238Abstract: A display assembly includes at least two display devices and two image compensating elements at a junction of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. Each image compensating element includes a light-incident surface on the display area, a light-emitting surface coupling to the light-incident surface, and a connecting surface coupling between the light-incident surface and the light-emitting surface. Each image compensating element includes a plurality of light guiding channels. Light guiding paths of the light guiding channels extend along a direction from the light-incident surface toward the light-emitting surface.Type: GrantFiled: March 19, 2019Date of Patent: July 28, 2020Assignee: SEAMLESS TECHNOLOGY INC.Inventors: I-Wei Wu, Chih-Lung Hung, Hsiao-Min Yin
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Publication number: 20200220372Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.Type: ApplicationFiled: March 18, 2020Publication date: July 9, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tau-Jing YANG, Kuo-Feng HUANG, Chih Lung HUNG
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Publication number: 20200209456Abstract: A display assembly includes at least two display devices and two image compensating elements at a junction of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. An optical axis direction of each of the image compensating elements is relatively toward above the juxtaposition of the adjacent two display devices. A light guiding sheet is positioned on the light-emitting surface of each of the image compensating elements; an optical axis direction of the light guiding sheet is perpendicular to the front surface.Type: ApplicationFiled: November 15, 2019Publication date: July 2, 2020Inventors: I-WEI WU, CHIH-LUNG HUNG
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Patent number: 10622836Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.Type: GrantFiled: May 2, 2017Date of Patent: April 14, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tau-Jing Yang, Kuo-Feng Huang, Chih Lung Hung
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Publication number: 20190318669Abstract: A display assembly includes at least two display devices and two image compensating elements at a juxtaposition of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. Each image compensating element includes a light-incident surface on the display area, a light-emitting surface coupling to the light-incident surface, and a connecting surface coupling between the light-incident surface and the light-emitting surface. Each image compensating element includes a plurality of light guiding channels. Light guiding paths of the light guiding channels curvedly extend along a direction from the light-incident surface toward the light-emitting surface.Type: ApplicationFiled: March 19, 2019Publication date: October 17, 2019Inventors: I-WEI WU, CHIH-LUNG HUNG, HSIAO-MIN YIN
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Publication number: 20190317274Abstract: A display assembly includes at least two display devices and two image compensating elements at a junction of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. Each image compensating element includes a light-incident surface on the display area, a light-emitting surface coupling to the light-incident surface, and a connecting surface coupling between the light-incident surface and the light-emitting surface. Each image compensating element includes a plurality of light guiding channels. Light guiding paths of the light guiding channels extend along a direction from the light-incident surface toward the light-emitting surface.Type: ApplicationFiled: March 19, 2019Publication date: October 17, 2019Inventors: I-WEI WU, CHIH-LUNG HUNG, HSIAO-MIN YIN
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Publication number: 20190317275Abstract: A display assembly includes at least two display devices and two image compensating elements at a junction of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Two front surfaces of adjacent two display devices intersect to form an angle of less than 180 degrees. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. Each image compensating element includes a light-incident surface covering the display area, a light-emitting surface coupling to the light-incident surface, and a connecting surface coupling between the light-incident surface and the light-emitting surface. Each image compensating element includes a plurality of light guiding channels. Light guiding paths of the light guiding channels extend along a direction from the light-incident surface toward the light-emitting surface.Type: ApplicationFiled: March 19, 2019Publication date: October 17, 2019Inventors: I-WEI WU, CHIH-LUNG HUNG
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Publication number: 20190212964Abstract: A display assembly includes at least two display devices and two image compensating elements at a junction of every adjacent two display devices. Each display device includes a front surface that is viewed by user. Two front surfaces of adjacent two display devices intersect to form an angle of less than 180 degrees. Each front surface defines a display area and a border area. Each image compensating element is on the front surface. Each image compensating element includes a light-incident surface covering the display area, a light-emitting surface coupling to the light-incident surface, and a connecting surface coupling between the light-incident surface and the light-emitting surface. Each image compensating element includes a plurality of light guiding channels. Light guiding paths of the light guiding channels curvedly extend along a direction from the light-incident surface toward the light-emitting surface.Type: ApplicationFiled: January 4, 2019Publication date: July 11, 2019Inventors: I-WEI WU, CHIH-LUNG HUNG
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Publication number: 20180323629Abstract: The present disclosure relates to a power management system. The power management system comprises a first power supply device, a second power supply device, a power supply control device, a data processing device and a load. The power supply control device is connected to the first power supply device. The data processing device is connected to the first power supply device, the second power supply device and the power supply control device. The load is connected to the first power supply device and the second power supply device. The power supply control device is configured to, when activated, provide a first signal to the data processing device. The data processing device is configured to select the first power supply device or the second power supply device to provide power to the load according to the first signal.Type: ApplicationFiled: May 2, 2017Publication date: November 8, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tau-Jing YANG, Kuo-Feng HUANG, Chih Lung HUNG
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Publication number: 20130105978Abstract: A silicon submount for a light emitting diode (LED) including a silicon base, a first insulating layer, a first electrode, a second electrode, and a reflective layer is provided. The silicon base has an upper surface and a lower surface, and a recess is disposed at the upper surface. The first insulating layer covers the upper surface and the lower surface of the silicon base. The first electrode and the second electrode are disposed on the first insulating layer on a bottom of the recess. The reflective layer is disposed on the first insulating layer on a sidewall of the recess. The first electrode, the second electrode, and the reflective layer are separated from one another and formed by the same material.Type: ApplicationFiled: December 26, 2011Publication date: May 2, 2013Applicant: EPISIL TECHNOLOGIES INC.Inventor: Chih-Lung Hung
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Patent number: 8021022Abstract: A lighting structure adapted to be disposed at an electronic apparatus is provided. The lighting structure includes a lighting module, a first elastic element, a latch, and a second elastic element. The lighting module has a light source and a stopper element. The first elastic element is connected to the lighting module. The latch has an interfering portion for blocking the stopper element and is capable of sliding in the electronic apparatus. The second elastic element is connected to the latch. When the latch is subjected to an external force and slides to deform the second elastic element, the stopper element disengages from the interfering portion, and the first elastic element rotates the lighting module, such that the lighting module is at a different position, and the light source is used to illuminate part of the electronic apparatus.Type: GrantFiled: July 10, 2008Date of Patent: September 20, 2011Assignee: Compal Electronics, Inc.Inventors: Kuo-Nan Ling, Wen-Wei Yang, Chih-Lung Hung, Wen-Chuan Su
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Patent number: 7715242Abstract: An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a first dielectric layer disposed on the floating gate, a second dielectric layer disposed on sidewalls of the floating gate, and an erase gate. The erasing method includes applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased.Type: GrantFiled: November 13, 2008Date of Patent: May 11, 2010Assignee: Episil Technologies Inc.Inventor: Chih-Lung Hung
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Publication number: 20100008096Abstract: A lighting structure adapted to be disposed at an electronic apparatus is provided. The lighting structure includes a lighting module, a first elastic element, a latch, and a second elastic element. The lighting module has a light source and a stopper element. The first elastic element is connected to the lighting module. The latch has an interfering portion for blocking the stopper element and is capable of sliding in the electronic apparatus. The second elastic element is connected to the latch. When the latch is subjected to an external force and slides to deform the second elastic element, the stopper element disengages from the interfering portion, and the first elastic element rotates the lighting module, such that the lighting module is at a different position, and the light source is used to illuminate part of the electronic apparatus.Type: ApplicationFiled: July 10, 2008Publication date: January 14, 2010Applicant: COMPAL ELECTRONICS, INC.Inventors: Kuo-Nan Ling, Wen-Wei Yang, Chih-Lung Hung, Wen-Chuan Su
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Patent number: 7560343Abstract: A manufacturing method of a non-volatile memory includes first providing a substrate for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; sequentially forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer without covering the first dielectric layer, and using the remained conductor layer as the floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate above the floating gate and correspondingly above the control gate, and forming a source region and a drain region in the other one of each pair of the active regions.Type: GrantFiled: November 13, 2008Date of Patent: July 14, 2009Assignee: Episil Technologies Inc.Inventor: Chih-Lung Hung
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Patent number: 7508028Abstract: A non-volatile memory is provided, including a control gate, a floating gate, a gate oxide layer, a source region, a drain region, a first dielectric layer, a second dielectric layer, and an erase gate. The control gate is disposed in a substrate. The floating gate comprising a coupling part and a gate part is disposed over the control gate and located over a portion of the substrate with the gate oxide layer there-between. The source region adjoins with one side of the gate part, while the drain region adjoins with the other side of the gate part. The first dielectric layer is disposed on the floating gate. The second dielectric layer is disposed on the sidewalls of the floating gate. The erase gate is disposed over the coupling part of the floating gate and covers the first dielectric layer and the second dielectric layer.Type: GrantFiled: October 26, 2006Date of Patent: March 24, 2009Assignee: Episil Technologies Inc.Inventor: Chih-Lung Hung
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Publication number: 20090059679Abstract: An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a first dielectric layer disposed on the floating gate, a second dielectric layer disposed on sidewalls of the floating gate, and an erase gate. The erasing method includes applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased.Type: ApplicationFiled: November 13, 2008Publication date: March 5, 2009Applicant: Episil Technologies Inc.Inventor: Chih-Lung Hung
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Publication number: 20090061582Abstract: A manufacturing method of a non-volatile memory includes first providing a substrate for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; sequentially forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer without covering the first dielectric layer, and using the remained conductor layer as the floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate above the floating gate and correspondingly above the control gate, and forming a source region and a drain region in the other one of each pair of the active regionsType: ApplicationFiled: November 13, 2008Publication date: March 5, 2009Applicant: Episil Technologies Inc.Inventor: Chih-Lung Hung