Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.

Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.

Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.

Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.

Abstract: A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.

Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.

Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.

Abstract: An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode.

Abstract: A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan lines includes a first scan line. The date lines are insulated with the scan lines include a first date line and a second date line. The first date line is insulated and at least partly covering the second date line. The pixels are defined by two adjacent scan lines and two adjacent date lines. The first TFT is configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line. The second TFT is configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line.

Abstract: A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.

Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

Abstract: A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.

Abstract: A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.

Abstract: A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.

Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.

Abstract: A method for manufacturing a thin film transistor (TFT), the TFT includes a gate, a first insulation layer, a channel layer, a source, a drain, a second insulation, and a flat layer. The gate is formed on a base. The first insulation layer is formed on the base to cover the gate and the base. The channel layer is formed on the first insulation layer corresponding to the gate. The second insulation layer is formed on the base to cover the first insulation layer, the channel layer, the source, and the drain. The flat layer includes a first region and a second region and is formed on the second insulation layer. The first region and the second region respectively have different light transmittance.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.

Abstract: A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.

Abstract: A method of manufacturing a thin film transistor substrate is provided, including a first photoresist pattern covers a channel during a process of etching a second photoresist pattern and protects the channel. Thus, an etching stop layer is not required.