Abstract: A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: A stacked flip-chip package comprises a substrate having an opening, a back-to-face chip module, and an encapsulant. The back-to-face chip module is attached to the substrate and encapsulated by the encapsulant. The back-to-face chip module includes a first chip and a second chip. The first chip has a first active surface and a first back surface. Redistributed traces are formed on the first back surface. The second chip is flip-chip mounted on the first back surface of the first chip and electrically connected to the redistributed traces. A plurality of bumps connect the redistributed traces to the top surface of the substrate. Thus the second chip can be accommodated inside the opening and the redistributed traces are electrically connected to the second chip and the substrate so as to achieve fine pitch flip-chip mounting and improve the electrical performance and heat dissipation efficiency for the back-to-face chip module.

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: A multi-chips stacked package mainly comprises a substrate, a lower chip, an upper chip and a supporter. The substrate has an upper surface, and the upper chip is disposed on the upper surface of the substrate and electrically connected to the substrate. The supporter has a carrying portion and at least a supporting portion connecting to the carrying portion and disposing on the substrate. In such a manner, the carrying portion covers the lower chip. Besides, the upper chip is disposed on the carrying portion of the supporter and electrically connected to the substrate.

Abstract: This invention provides a method for manufacturing a semiconductor chip package which mainly utilizes a substrate having a organic surface protection thereon to package a central-pad chip. In the encapsulating process, since the molding flash is completely formed on the surface of the organic surface protection, the molding flash can be easily removed together with the organic surface protection without damaging the substrate surface. This invention further provides a method for manufacturing the substrate.

Abstract: This invention provides a method for manufacturing a semiconductor chip package which mainly utilizes a substrate having a organic surface protection thereon to package a central-pad chip. In the encapsulating process, since the molding flash is completely formed on the surface of the organic surface protection, the molding flash can be easily removed together with the organic surface protection without damaging the substrate surface. This invention further provides a method for manufacturing the substrate.

Abstract: A chip stack-type semiconductor package comprises: a substrate having a through hole penetrating there through, the substrate further having a plurality of first mounting pads and a plurality of second mounting pads; a first chip having a plurality of first bonding pads; a second chip having a plurality of second bonding pads, a backside surface of the second chip adhered onto a backside surface of the first chip, a active surface of the second chip adhered onto the substrate, the second bonding pads exposed to the inside of the through hole of the substrate; a plurality of first wires, connecting the first bonding pads and the first mounting pads; a plurality of second wires, connecting the second bonding pads and the second mounting pads; and a molding compound enveloping the first chip, the second chip, the first wires and the second wires.

Abstract: A method for detecting the position of a wafer in the slot of a wafer boat. The method comprises: Providing a first light source and second light source. Using a beam splitter apparatus for separating the light emitted from the first light source into a first light beam and a second light beam. Using a first sensor to receive the first light beam and functions in detecting the existence of the wafer in the slot of the wafer boat. Using a second sensor to receive the second light beam and functions in detecting the number of wafers in the slot of the wafer boat. Using a third sensor to receive the light emitted from the second light source to detect whether there is a protrusion of the wafer from the wafer boat.

Abstract: A substrate structure mainly comprises a plurality of substrate units and a plurality of dispensing holes thereon. A main hole is provided on the surface of the substrate unit, the two ends of which are adjacent to the dispensing hole for dispensing liquified encapsulant material to form a semiconductor package. The semiconductor package mainly comprises a chip, a substrate and an encapsulant. The chip is adhesively attached to the substrate, and the encapsulant covers around the are along one side of the chip. Then the encapsulant flows from the upper surface of the substrate to the lower surface to cover wire areas by means of the liquified encapsulant material flowing through the dispensing hole from the upper surface of the substrate to the lower surface.

Abstract: A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.