Abstract: Methods and systems for generating an entity diagram include, in one exemplary embodiment, a user using a processor that executes the program code to generate the entity diagram. The process for generating the entity diagram includes generating an entity diagram with one or more entities and one or more relationships, grouping the one or more entities by a first dimension, and grouping the one or more entities by a second dimension. The process further includes rearranging the groups based on the grouping according to the first dimension, rearranging the entities based on the grouping according to the second dimension, and adjusting one or more relationship links corresponding to the one or more relationships. After the one or more entities and relationships are rearranged and adjusted, the user may access an updated entity diagram.

Abstract: A system includes a memory to store program code and a processor to execute the program code to perform a process for generating a business intelligence (BI) data presentation. The process includes collecting BI data from one or more data sources and verifying the collected BI data. The process further includes defining an output presentation format in a multidimensional BI database, loading the collected BI data into the multidimensional BI database, refreshing data tables in the multidimensional BI database based on the loaded set of BI data, and generating an output BI data presentation based on the loaded BI data and the output presentation format.

Abstract: Methods and systems for generating an entity diagram include, in one exemplary embodiment, a user using a processor that executes the program code to generate the entity diagram. The process for generating the entity diagram includes generating an entity diagram with one or more entities and one or more relationships, grouping the one or more entities by a first dimension, and grouping the one or more entities by a second dimension. The process further includes rearranging the groups based on the grouping according to the first dimension, rearranging the entities based on the grouping according to the second dimension, and adjusting one or more relationship links corresponding to the one or more relationships. After the one or more entities and relationships are rearranged and adjusted, the user may access an updated entity diagram.

Abstract: According to one embodiment, a CAM system (100) may include a comparand register (CMPR) index block (106) for monitoring a status of comparand registers within the CAM blocks (104). A CMPR index block (106) may include a free index register set (120). A free head pointer (122) and a free tail pointer (124) can point to a start and end of a list of free comparand index values stored within a free index register set (120). A CMPR index block (106) may also include a busy index register set (126). A busy head pointer (128) and a busy tail pointer (130) can point to a start and end of a list of busy comparand index values stored within a busy index register set (126).

Abstract: An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) circuit uses a memory map which accommodates a variety of memory sizes. The SAR circuit generates address signals according to the memory map which is independent of memory size. The most significant bits (MSBs) of the address are ignored for memories having fewer address terminals than the SAR circuit. The memory map allocates N-bit addresses to buffers and an expansion area. A first buffer has addresses with i+1 MSBs set to 1 and a second buffer has addresses with i+1 MSBs set to 0. i MSBs can be ignored without causing address conflicts because an address for the first buffer has at least one bit that differs from a corresponding bit in an address for the second buffer. The first and second buffers expand, as required, into the expansion area between the buffer. For an application using the smallest memory, conflicts do not occur because the first and second buffers are sufficient for the minimum memory applications.

Abstract: A segmentation and reassembly circuit under the ATM standard uses a transmit cell schedule table (TCST) to support real time transmission of ATM cells in multiple constant bit rate virtual channels. In one embodiment, null cells are intentionally scheduled in a TCST. Transmission of the scheduled null cells ("forced null cells") or non-time critical cells are skipped to compensate for delays in an ATM cell transmission schedule, e.g. delays due to a bus latency. During such latency, null cells are generated from a null cell generator and a negative credit counter is incremented for each ATM cell transmission time missed. When transmission of a forced null cell is skipped, the negative credit counter is decremented.