Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a first edge and a second edge extending along a first direction; and a plurality of patterns on the substrate extending along the first direction, in which the patterns includes a plurality of first patterns and a plurality of second patterns, and one of the first patterns closest to the first edge and one of the second patterns closest to the second edge are different.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.

Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.