Patents by Inventor Chih-Tsung Shih
Chih-Tsung Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230314719Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
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Publication number: 20230314718Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit. The integrated circuit includes a substrate having an upper face and a lower face. The upper face includes a central region and an outer sidewall that laterally surrounds the central region and that extends from the upper face to the lower face. An optical edge coupler is disposed over the upper face of the substrate and extends in a first direction from the central region toward the outer sidewall. An outer sidewall of the optical edge coupler corresponds to the outer sidewall of the substrate and has a concave surface or a convex surface.Type: ApplicationFiled: July 1, 2022Publication date: October 5, 2023Inventors: Wei-Kang Liu, Chih-Tsung Shih, Hau-Yan Lu, Yingkit Felix Tsui
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Patent number: 11774844Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.Type: GrantFiled: March 14, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Tsung Shih, Tsung-Chih Chien, Shih-Chi Fu, Chi-Hua Fu, Kuotang Cheng, Bo-Tsun Liu, Tsung Chuan Lee
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Publication number: 20230296846Abstract: Disclosed are apparatus and methods for optical coupling.Type: ApplicationFiled: May 23, 2023Publication date: September 21, 2023Inventors: Chih-Tsung SHIH, Chewn-pu JOU, Stefan RUSU, Felix Ying-Kit TSUI, Lan-Chou CHO
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Publication number: 20230280527Abstract: An optical device includes an input array, an output array and a waveguide array. The input array is connected to a first slab structure, while the output array is connected to a second slab structure. The waveguide array is optically coupled to the first slab structure and the second slab structure. The waveguide array includes a first connecting part, a second connecting part and a plurality of waveguide channels. The first connecting part is joined with the first slab structure. The second connecting part is joined with the second slab structure, wherein the second connecting part includes a central portion and at least one flank portion, the central portion is connected to and overlapped with the second slab structure, and the at least one flank portion extends over a side surface of the second slab structure. The waveguide channels are joining the first connecting part to the second connecting part.Type: ApplicationFiled: May 10, 2023Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tsung Shih, Felix Yingkit Tsui, Stefan Rusu, Chewn-Pu Jou
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Publication number: 20230273367Abstract: Various embodiments of the present disclosure are directed towards a semiconductor package comprising optically coupled integrated circuit (IC) chips. A first IC chip and a second IC chip overlie a substrate at a center of the substrate. A photonic chip overlies the first and second IC chips and is electrically coupled to the second IC chip. A laser device chip overlies the substrate, adjacent to the photonic chip and the second IC chip, at a periphery of the substrate. The photonic chip is configured to modulate a laser beam from the laser device chip in accordance with an electrical signal from the second IC chip and to provide the modulated laser beam to the first IC chip. This facilitates optical communication between the first IC chip to the second IC chip. Various embodiments of the present disclosure are further directed towards simultaneously aligning and bonding constituents of the semiconductor package.Type: ApplicationFiled: May 23, 2022Publication date: August 31, 2023Inventors: Chih-Tsung Shih, Hau-Yan Lu, Wei-Kang Liu, Yingkit Felix Tsui
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Patent number: 11720025Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.Type: GrantFiled: June 23, 2022Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Tsung Shih, Yu-Hsun Wu, Bo-Tsun Liu, Tsung-Chuan Lee
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Patent number: 11714239Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.Type: GrantFiled: July 26, 2022Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
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Publication number: 20230236498Abstract: A reticle enclosure includes a base including a first surface, a cover including a second surface and coupled to the base with the first surface facing the second surface. The base and the cover form an internal space that includes a reticle. The reticle enclosure includes restraining mechanisms arranged in the internal space and for securing the reticle, and structures disposed adjacent the reticle in the internal space. The structures enclose the reticle at least partially, and limit passage of contaminants between the internal space and an external environment of the reticle enclosure. The structures include barriers disposed on the first and second surfaces. In other examples, a padding is installed in gaps between the barriers and the first and second surfaces. In other examples, the structures include wall structures disposed on the first and second surfaces and between the restraining mechanisms.Type: ApplicationFiled: March 27, 2023Publication date: July 27, 2023Inventors: Chih-Tsung SHIH, Tsung-Chih CHIEN, Tsung Chuan LEE, Hao-Shiang CHANG
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Patent number: 11703762Abstract: A method of generating a layout pattern includes disposing a photoresist layer of a resist material on a substrate and disposing a top layer over of the photoresist layer. The top layer is transparent for extreme ultraviolet (EUV) radiation and the top layer is opaque for deep ultraviolet (DUV) radiation. The method further includes irradiating the photoresist layer with radiation generated from an EUV radiation source. The radiation passes through the top layer to expose the photoresist layer.Type: GrantFiled: October 24, 2019Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Tsung Shih, Chen-Ming Wang, Yahru Cheng, Bo-Tsun Liu, Tsung Chuan Lee
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Patent number: 11693186Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a described apparatus includes: a planar layer; a grating region comprising an array of scattering elements arranged in the planar layer to form a two-dimensional grating; a first taper structure formed in the planar layer connecting a first side of the grating region to a first waveguide, wherein a shape of the first taper structure is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region in the planar layer; and a second taper structure formed in the planar layer connecting a second side of the grating region to a second waveguide, wherein a shape of the second taper structure is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region in the planar layer, wherein the first side and the second side are substantially perpendicular to each other.Type: GrantFiled: April 1, 2021Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Tsung Shih, Chewn-Pu Jou, Stefan Rusu, Felix Ying-Kit Tsui, Lan-Chou Cho
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Patent number: 11686900Abstract: An optical device includes an input array, an output array and a waveguide array. The input array is connected to a first slab structure, while the output array is connected to a second slab structure. The waveguide array is optically coupled to the first slab structure and the second slab structure. The waveguide array includes a first connecting part, a second connecting part and a plurality of waveguide channels. The first connecting part is joined with the first slab structure. The second connecting part is joined with the second slab structure, wherein the second connecting part includes a central portion and at least one flank portion, the central portion is connected to and overlapped with the second slab structure, and the at least one flank portion extends over a side surface of the second slab structure. The waveguide channels are joining the first connecting part to the second connecting part.Type: GrantFiled: March 11, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tsung Shih, Felix Yingkit Tsui, Stefan Rusu, Chewn-Pu Jou
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Patent number: 11657492Abstract: A method of inspecting a reticle includes obtaining a first image of a surface of the reticle at a first height by scanning the reticle surface with a light source at the first height of the reticle surface relative to a reference surface height of the reticle surface and obtaining a second image of the reticle surface at a second height by scanning the reticle surface with the light source at the second height of the reticle surface relative to the reference surface height of the reticle surface. The second height is different from the first height. The first and the second images are then combined to obtain a surface profile image of the reticle.Type: GrantFiled: May 3, 2021Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zi-Wen Chen, Po-Chung Cheng, Chih-Tsung Shih, Li-Jui Chen, Shih-Chang Shih
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Publication number: 20230152713Abstract: A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer over a wafer stage. The method also includes supplying an initial voltage to a plurality of electrodes of the wafer stage based on a topology of the semiconductor wafer, wherein the electrodes of the wafer stage are electrically isolated from each other. The method further includes measuring an adjusted topology of the semiconductor wafer after the initial voltage is supplied. In addition, the method includes supplying different first adjusted voltages to the electrodes of the wafer stage according to the adjusted topology of the semiconductor wafer.Type: ApplicationFiled: January 9, 2023Publication date: May 18, 2023Inventors: Cheng-Kuan WU, Po-Chung CHENG, Li-Jui CHEN, Chih-Tsung SHIH
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Patent number: 11614683Abstract: A reticle enclosure includes a base including a first surface, a cover including a second surface and coupled to the base with the first surface facing the second surface. The base and the cover form an internal space that includes a reticle. The reticle enclosure includes restraining mechanisms arranged in the internal space and for securing the reticle, and structures disposed adjacent the reticle in the internal space. The structures enclose the reticle at least partially, and limit passage of contaminants between the internal space and an external environment of the reticle enclosure. The structures include barriers disposed on the first and second surfaces. In other examples, a padding is installed in gaps between the barriers and the first and second surfaces. In other examples, the structures include wall structures disposed on the first and second surfaces and between the restraining mechanisms.Type: GrantFiled: July 21, 2022Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Tsung Shih, Tsung-Chih Chien, Tsung Chuan Lee, Hao-Shiang Chang
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Publication number: 20230073062Abstract: A method for preventing photomask contamination includes securing a photomask on a bottom surface of an electrostatic chuck; generating a first voltage at a peripheral area of the bottom surface of the electrostatic chuck to attract a particle onto the peripheral area of the bottom surface of the electrostatic chuck, wherein the peripheral area of the bottom surface of the electrostatic chuck is not directly above the photomask; after generating the first voltage, generating a second voltage at the peripheral area of the bottom surface of the electrostatic chuck to repulse the particle, wherein the first voltage and the second voltage have opposite electrical properties; and generating a third voltage, by using a collecting plate, near a sidewall of the photomask to attract the repulsed particle.Type: ApplicationFiled: November 16, 2022Publication date: March 9, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Chieh CHEN, Tsung-Chih CHIEN, Chih-Tsung SHIH, Tsung-Chuan LEE
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Patent number: 11594528Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.Type: GrantFiled: May 26, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
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Patent number: 11550228Abstract: A lithography apparatus is provided. The lithography apparatus includes a wafer stage configured to secure a semiconductor wafer and having a plurality of electrodes. The lithography apparatus also includes an exposure tool configured to perform an exposure process by projecting an extreme ultraviolet (EUV) light on the semiconductor wafer. The lithography apparatus further includes a controller configured to control power supplied to the electrodes to have a first adjusted voltage during the exposure process for a first group of exposure fields on the semiconductor wafer so as to secure the semiconductor wafer to the wafer stage. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.Type: GrantFiled: March 26, 2021Date of Patent: January 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Kuan Wu, Po-Chung Cheng, Li-Jui Chen, Chih-Tsung Shih
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Publication number: 20220382005Abstract: Disclosed are apparatus and methods for optical interconnections that include the integration of a photonics die @Die) and an electronic die (eDie) with a socket layer, waveguides and fiber connectors to enable high bandwidth communications. In one embodiment, an exemplary optical interconnect device includes an electronic die coupled to a photonics die and integrated with a substrate, a socket, a board, a pair of micro-lenses and a mirror coupled to a waveguide, which can be embedded in the board. In another embodiment, the waveguide is embedded in a socket layer and coupled to a fiber connector. In these embodiments, the exemplary optical interface device can be coupled one more other optical interconnect devices via a waveguide array and/or a fiber array.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Inventors: Stefan RUSU, Wei-wei SONG, Mohammed Rabiul ISLAM, Chih-Tsung SHIH
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Publication number: 20220373890Abstract: A method of generating a layout pattern includes disposing a photoresist layer of a resist material on a substrate and disposing a top layer over of the photoresist layer. The top layer is transparent for extreme ultraviolet (EUV) radiation and the top layer is opaque for deep ultraviolet (DUV) radiation. The method further includes irradiating the photoresist layer with radiation generated from an EUV radiation source. The radiation passes through the top layer to expose the photoresist layer.Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Inventors: Chih-Tsung SHIH, Chen-Ming WANG, Yahru CHENG, Bo-Tsun LIU, Tsung Chuan LEE