Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

Abstract: A mass transfer method, a mass transfer device and a buffer carrier are provided. The mass transfer method includes: (a) providing a plurality of electronic components disposed on a source carrier; (b) providing a buffer carrier including a plurality of adjusting cavities; and (c) transferring the electronic components from the source carrier to the buffer carrier, wherein the electronic components are placed in the adjusting cavities of the buffer carrier to adjust positions of the electronic components from shifted positions to correct positions.

Abstract: A destructive packaging container is disclosed herein. It comprises a case body having a recessed groove around an opening at a top thereof, a case lid having a protrusion around a periphery thereof for engaging with the recessed groove, wherein an outer edge of one end of the recessed groove and an outer edge of one end of the protrusion are respectively extended with at least one force-applied ear staggered from each other; two connecting strips disposed at two sides of the at least one force-applied ear at the one end of the recessed groove for connecting the outer edge of the one end of the protrusion; and two cutting lines disposed at a junction of the two connecting strips and the case lid.

Abstract: The present invention provides an operational-task-oriented system and method for dynamically adjusting operational environment applicable to a computer cluster. Each operational node of the computer cluster has two or more operational systems installed. After receiving the operational task, the control node estimates the time required for completing different tasks requiring different operational systems by appropriate operational nodes and compares the estimated finish time and the assigned finish time for judging how to adjust the operating system running in the operational nodes. Thereby, the operational task can be completed in the assigned finish time. Another method is to use the control node to analyze the proportions of the tasks requiring different operational systems in an operational task and hence adjusts the operational system running in an operational node according to the proportion of requirement. Thereby, the operational task can be completed in the shortest time.

Abstract: The present invention provides an operational-task-oriented system and method for dynamically adjusting operational environment applicable to a computer cluster. Each operational node of the computer cluster has two or more operational systems installed. After receiving the operational task, the control node estimates the time required for completing different tasks requiring different operational systems by appropriate operational nodes and compares the estimated finish time and the assigned finish time for judging how to adjust the operating system running in the operational nodes. Thereby, the operational task can be completed in the assigned finish time. Another method is to use the control node to analyze the proportions of the tasks requiring different operational systems in an operational task and hence adjusts the operational system running in an operational node according to the proportion of requirement. Thereby, the operational task can be completed in the shortest time.

Abstract: Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve.

Abstract: A method for avoiding unnecessary excessive stay of short cycle in discontinuous reception mechanism begins by using the short cycle while the short cycle timer is running. Then, it determines whether the inactivity timer expires or not and whether the short cycle timer expires or not. If the inactivity timer expires but the short cycle timer does not expire, the short cycle is used. If the short cycle timer expires but the inactivity timer does not expire, the long cycle is used. If the inactivity timer and the short cycle timer expire at the same time, either the short cycle or the long cycle is selected for use.

Abstract: Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve.

Abstract: A method for avoiding unnecessary excessive stay of short cycle in discontinuous reception mechanism begins by using the short cycle while the short cycle timer is running. Then, it determines whether the inactivity timer expires or not and whether the short cycle timer expires or not. If the inactivity timer expires but the short cycle timer does not expire, the short cycle is used. If the short cycle timer expires but the inactivity timer does not expire, the long cycle is used. If the inactivity timer and the short cycle timer expire at the same time, either the short cycle or the long cycle is selected for use.

Abstract: A fastening mechanism for a package device is provided, which includes a plurality of first protrusions stagger-arranged in two rows at an edge of a lid of the package device, wherein a gap is formed between the two rows of the first protrusions; a second protrusion formed on an edge of a body of the package device and corresponding in position to the gap; at least a projection formed on the edge of the body and substantially opposed in position to the second protrusion; and at least a recess formed on the edge of the lid and corresponding in position to the projection of the body. By coupling the lid to the body, the second protrusion is engaged with the gap between the first protrusions, and the projection of the body is engaged with the recess of the lid, so as to provide strong fastening effect for the package device.

Abstract: An electromotive gear-shift control apparatus for bicycles, which is to be used in a bicycle provided with a gear-shift apparatus; the driving force for such apparatus is furnished with the power of pedals thereof; a motor is used for determining the input of the gear shift; the apparatus comprises a housing, a transmission mechanism, a switch mechanism, and an index mechanism; the housing is a fixed member fastened on the frame of a bicycle; the power source for gear shift is supplied by the driving force of the power shaft between two pedals of bicycle; the switch mechanism is mounted in the housing; the input power form the transmission mechanism is converted, by means of the motor, into a displacement output required by gear shift; the index mechanism is mounted behind the switch mechanism inside the housing, and it is used for converting the vector displacement form the switch mechanism into a step-function output, which is then transmitted, through a cable, into the gear-shift apparatus of the bicycle.