Patents by Inventor Chih Wen Hsu

Chih Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985314
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing out-of-bounds nodes in a current picture. An out-of-bounds node is a coding tree node with a block region across a current picture boundary. The video processing method or apparatus determines an inferred splitting type, applies the inferred splitting type to split the out-of-bounds node into child blocks, adaptively splits each child block into one or multiple leaf blocks, and encodes or decodes the leaf blocks in the out-of-bounds node inside the current picture. The inferred splitting type for partitioning out-of-bounds nodes in an inter slice, picture, or tile is the same as the inferred splitting type for partitioning out-of-bounds nodes in an intra slice, picture, or tile.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Patent number: 11985324
    Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 14, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11979613
    Abstract: Encoding methods and apparatuses include receiving input video data of a current block in a current picture and applying a Cross-Component Adaptive Loop Filter (CCALF) processing on the current block based on cross-component filter coefficients to refine chroma components of the current block according to luma sample values. The method further includes signaling two Adaptive Loop Filter (ALF) signal flags and two CCALF signal flags in an Adaptation Parameter Set (APS) with an APS parameter type equal to ALF or parsing two ALF signal flags and two CCALF signal flags from an APS with an APS parameter type equal to ALF, signaling or parsing one or more Picture Header (PH) CCALF syntax elements or Slice Header (SH) CCALF syntax elements, wherein both ALF and CCALF signaling are present either in a PH or SH, and encoding or decoding the current block in the current picture.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: May 7, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Ching-Yeh Chen, Olena Chubach, Chen-Yen Lai, Tzu-Der Chuang, Chih-Wei Hsu, Yu-Wen Huang
  • Patent number: 11979593
    Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 7, 2024
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chun Chiu, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
  • Publication number: 20240145398
    Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
  • Patent number: 11973985
    Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 30, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Patent number: 11967717
    Abstract: Disclosed is a tungsten-doped lithium manganese iron phosphate-based particulate for a cathode of a lithium-ion battery. The particulates include a composition represented by a formula of LixMn0.998-y-zFeyMzW0.002PaO4a±p/C, wherein x, y, z, a, p, and M are as defined herein. Also disclosed is a powdery material including the particulates, and a method for preparing the powdery material.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: April 23, 2024
    Assignee: HCM CO., LTD.
    Inventors: Chien-Wen Jen, Hsin-Ta Huang, Chih-Tsung Hsu, Yi-Hsuan Wang
  • Patent number: 11956421
    Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Publication number: 20240114688
    Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 4, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240088187
    Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 14, 2024
    Inventors: Chih Cheng Shih, Tsun-Kai Tsao, Jiech-Fun Lu, Hung-Wen Hsu, Bing Cheng You, Wen-Chang Kuo
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11916151
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Ming Hsu, Yi-Jing Li, Chih-Hsin Ko, Kuang-Hsin Chen, Da-Wen Lin, Clement Hsingjen Wann
  • Patent number: 11917185
    Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 27, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20240027739
    Abstract: An imaging lens assembly includes a lens element and a light blocking element. The lens element is configured to define an optical axis, and the optical axis passes through the lens element. The light blocking element includes a light through hole and a plurality of light diminishing structures. The optical axis passes through the light through hole, the light through hole is formed by connecting a plurality of sidelines to define a polygonal contour. The light diminishing structures are regularly disposed along the polygonal contour, wherein the light diminishing structures are configured to undulate at least one portion of each of the sidelines, so that the at least one portion of each of the sidelines is a non-straight line.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 25, 2024
    Inventors: Chih-Wen HSU, Chen-Wei FAN, Ming-Ta CHOU
  • Publication number: 20230358992
    Abstract: An imaging lens assembly, having an optical axis, includes an imaging lens set and a lens holding member. The lens holding member accommodates the imaging lens set for aligning the imaging lens set with the optical axis. The lens holding member includes a plurality of light-blocking structures, which are disposed on an object side of the imaging lens set and surround the optical axis for forming a light passing hole. Each of the light-blocking structures is a straight-line shape and has two end points and one central point, and the central point is closer to the optical axis than each of the two end points thereto. A maximum radius of the light passing hole is defined by a position near each of the two end points, and a minimum radius thereof is defined by a position near the central point.
    Type: Application
    Filed: March 21, 2023
    Publication date: November 9, 2023
    Inventors: Chih-Wen HSU, Heng-Yi SU, Chun-Jui PAN, Ming-Ta CHOU
  • Publication number: 20230333291
    Abstract: A light blocking sheet having a central axis includes a central hole and a plurality of inner extended portions. The central axis passes through the central hole, which is enclosed by a hole inner surface. The hole inner surface has a first corresponding circle and a second corresponding circle, wherein a diameter of the first corresponding circle is greater than a diameter of the second corresponding circle. The inner extended portions are adjacent to and surround the central hole, wherein each of the inner extended portions is extended and tapered from the first corresponding circle towards the second corresponding circle and includes an inner surface, and the inner surface includes a line pair. The line pair includes two line sections, wherein one end of one line section thereof and one end of the other line section thereof are towards the second corresponding circle and approach to each other.
    Type: Application
    Filed: June 19, 2023
    Publication date: October 19, 2023
    Inventors: Ming-Ta CHOU, Ming-Shun CHANG, Chih-Wen HSU
  • Publication number: 20230324645
    Abstract: An imaging lens assembly includes a plurality of optical lens elements, a single-piece-formed light blocking sheet and a lens barrel. The lens barrel has a circular light-passing hole corresponding to the plurality of optical lens elements and the single-piece-formed light blocking sheet. The single-piece-formed light blocking sheet has a central aperture corresponding to the lens barrel and the plurality of optical lens elements. A maximum aperture diameter is defined by the central aperture. The single-piece-formed light blocking sheet comprises a plurality of light blocking structures surrounding and disposed adjacent to the central aperture. A minimum inner radius of the central aperture is defined near the center of each of the light blocking structures.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 12, 2023
    Inventors: Chih-Wen HSU, Hsiu-Yi HSIAO, Ming-Ta CHOU
  • Patent number: 11719863
    Abstract: A light blocking sheet having a central axis includes a central hole and a plurality of inner extended portions. The central axis passes through the central hole, which is enclosed by a hole inner surface. The hole inner surface has a first corresponding circle and a second corresponding circle, wherein a diameter of the first corresponding circle is greater than a diameter of the second corresponding circle. The inner extended portions are adjacent to and surround the central hole, wherein each of the inner extended portions is extended and tapered from the first corresponding circle towards the second corresponding circle and includes an inner surface, and the inner surface includes a line pair. The line pair includes two line sections, wherein one end of one line section thereof and one end of the other line section thereof are towards the second corresponding circle and approach to each other.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 8, 2023
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Ming-Ta Chou, Ming-Shun Chang, Chih-Wen Hsu