Patents by Inventor Chih-Yao Chen
Chih-Yao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11997798Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.Type: GrantFiled: August 30, 2022Date of Patent: May 28, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
-
Publication number: 20240170543Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
-
Publication number: 20240170336Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
-
Publication number: 20240154025Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metalType: ApplicationFiled: January 10, 2024Publication date: May 9, 2024Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
-
Patent number: 11973985Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.Type: GrantFiled: August 22, 2022Date of Patent: April 30, 2024Assignee: MediaTek Inc.Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
-
Patent number: 11955385Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.Type: GrantFiled: August 27, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Hsiao Wen Lee
-
Patent number: 11942363Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.Type: GrantFiled: August 9, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
-
Publication number: 20240096893Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
-
Patent number: 11923440Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.Type: GrantFiled: July 26, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
-
Patent number: 9279853Abstract: A test probe card structure includes a probe card and a connection circuit common plate. The probe card includes a probe substrate, A test circuit board is disposed between the probe substrate and the connection circuit common plate, The test circuit board has a lest circuit connection section attached to and electrically connected with a common circuit adaptation section of the connection circuit common plate. A circuit extension section is formed around the connection circuit common plate, which is all-channel electrically connectable between a tester and the teat circuit connection section. The connection circuit common plate serves to provide an all-channel test circuit convergence connection ability for the test circuit board so as to greatly minify the size of the test circuit board and lower the manufacturing cost of the probe card.Type: GrantFiled: July 30, 2014Date of Patent: March 8, 2016Assignee: Hermes-Epitek Corp.Inventors: Chien-Yao Hung, Chih-Yao Chen
-
Publication number: 20140340109Abstract: A test probe card structure includes a probe card and a connection circuit common plate. The probe card includes a probe substrate, A test circuit board is disposed between the probe substrate and the connection circuit common plate, The test circuit board has a lest circuit connection section attached to and electrically connected with a common circuit adaptation section of the connection circuit common plate. A circuit extension section is formed around the connection circuit common plate, which is all-channel electrically connectable between a tester and the teat circuit connection section. The connection circuit common plate serves to provide an all-channel test circuit convergence connection ability for the test circuit board so as to greatly minify the size of the test circuit board and lower the manufacturing cost of the probe card.Type: ApplicationFiled: July 30, 2014Publication date: November 20, 2014Inventors: CHIEN-YAO HUNG, CHIH-YAO CHEN
-
Patent number: 8829936Abstract: A probe card structure adaptable to different test apparatuses of different specifications includes a probe card adapted to a first specification, a reinforcement member adapted to a second specification and a specification conversion interface unit disposed between the probe card and the reinforcement member. The probe card without the specification conversion interface unit can be directly mounted on a test apparatus of the first specification by means of a reinforcement member of the first specification to carry out the test process. Alternatively, the specification conversion interface unit can be combined with the probe card to convert the probe card from the first specification to the second specification. Accordingly, the probe card of the second specification can be mounted on a test apparatus of the second specification by means of the reinforcement member of the second specification to carry out the test process.Type: GrantFiled: May 25, 2011Date of Patent: September 9, 2014Assignee: Hermes-Epitek Corp.Inventors: Chien-Yao Hung, Chih Yao Chen
-
Publication number: 20120049878Abstract: A probe card structure adaptable to different test apparatuses of different specifications includes a probe card adapted to a first specification, a reinforcement member adapted to a second specification and a specification conversion interface unit disposed between the probe card and the reinforcement member. The probe card without the specification conversion interface unit can be directly mounted on a test apparatus of the first specification by means of a reinforcement member of the first specification to carry out the test process. Alternatively, the specification conversion interface unit can be combined with the probe card to convert the probe card from the first specification to the second specification. Accordingly, the probe card of the second specification can be mounted on a test apparatus of the second specification by means of the reinforcement member of the second specification to carry out the test process.Type: ApplicationFiled: May 25, 2011Publication date: March 1, 2012Applicant: HERMES TESTING SOLUTIONS, INC.Inventors: CHIEN-YAO HUNG, CHIH YAO CHEN
-
Patent number: 6000769Abstract: A computer front cover mounting arrangement includes two doorposts fixedly fastened to two opposite vertical lateral sides of the face panel of a computer mainframe, each door post having two pivot shafts at top and bottom sides, and a front cover releasably coupled to the doorposts and covered on the face panel and selectively openable from the face panel from the left side or the right side, the front cover having backward coupling flanges in four corners, each coupling flange having a circular recess for coupling with one pivot shaft, and a guide groove for guiding the corresponding pivot shaft into coupling position.Type: GrantFiled: October 22, 1998Date of Patent: December 14, 1999Assignee: Enlight CorporationInventor: Chih-Yao Chen
-
Patent number: 5785154Abstract: A type of wheel with a brake device is devised which consists of 2 corresponding housings. A curved trough is facilitated between the inner and outer edges of one of the 2 housings; the curve trough containing a shaft. One end of the shaft touches the inner side of the curved trough whereas the other end touches the inner side of the other housing. The two lateral sides of a secure mount fit over the two lateral sides of the wheel; a wheel axle is inserted through the mount and the housings to form the wheel. A joining device is facilitated at the outer end of the axle which functions to connect the device to other objects such as vehicles, chairs, toddler chairs, etc.Type: GrantFiled: February 20, 1997Date of Patent: July 28, 1998Assignee: Kingstar Baby Carriages, Co., Ltd.Inventor: Chih-Yao Chen