Patents by Inventor Chih-Yao Lin
Chih-Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170543Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
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Publication number: 20240170336Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Publication number: 20240169394Abstract: A blockchain-based member tracking system, communicatively connected to multiple web servers and multiple user devices, comprises an advertising database, multiple advertising modules, a primary member database, and a blockchain module. The advertising modules are configured to run on the web servers and are configured for displaying the advertising data. When the user device connects to the web server, the blockchain module generates a set of the preference tags and a set of the point data, and associates them with the corresponding member data of the user device. When the user device connects to the web server, the advertising module selects the advertising data based on the corresponding member data and the preference tags. The preference tags are a form of non-fungible token data.Type: ApplicationFiled: November 20, 2023Publication date: May 23, 2024Applicant: AVIVID INNOVATIVE MEDIA CO., LTDInventors: Yu Ju Tang, Chih-Yao Lin
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Publication number: 20240153827Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.Type: ApplicationFiled: January 2, 2024Publication date: May 9, 2024Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Shu-Yuan Ku
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Publication number: 20240154025Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metalType: ApplicationFiled: January 10, 2024Publication date: May 9, 2024Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 11965217Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.Type: GrantFiled: May 24, 2021Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
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Patent number: 11955385Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.Type: GrantFiled: August 27, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Hsiao Wen Lee
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Patent number: 11942396Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.Type: GrantFiled: December 29, 2021Date of Patent: March 26, 2024Assignee: Industrial Technology Research InstituteInventors: Heng-Chieh Chien, Shu-Jung Yang, Yu-Min Lin, Chih-Yao Wang, Yu-Lin Chao
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Patent number: 11942363Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.Type: GrantFiled: August 9, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Patent number: 11942529Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.Type: GrantFiled: June 7, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
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Publication number: 20240096893Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
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Publication number: 20240097007Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Hsiao Wen Lee, Ya-Yi Tsai, Shu-Uei Jang, Chih-Han Lin, Shu-Yuan Ku
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Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Patent number: 11923440Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.Type: GrantFiled: July 26, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
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Patent number: 11552245Abstract: A conductive bridge random access memory and its manufacturing method are provided. The conductive bridge random access memory includes a bottom electrode, an inter-metal dielectric, a resistance switching assembly, and a top electrode. The bottom electrode is disposed on a substrate, and the inter-metal dielectric is disposed above the bottom electrode. The resistance switching assembly is disposed on the bottom electrode and positioned in the inter-metal dielectric. The resistance switching assembly has a reverse T-shape cross-section. The top electrode is disposed on the resistance switching assembly and the inter-metal dielectric.Type: GrantFiled: February 27, 2020Date of Patent: January 10, 2023Assignee: WINDBOND ELECTRONICS CORP.Inventors: Chih-Yao Lin, Po-Yen Hsu, Bo-Lun Wu
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Publication number: 20210273159Abstract: A conductive bridge random access memory and its manufacturing method are provided. The conductive bridge random access memory includes a bottom electrode, an inter-metal dielectric, a resistance switching assembly, and a top electrode. The bottom electrode is disposed on a substrate, and the inter-metal dielectric is disposed above the bottom electrode. The resistance switching assembly is disposed on the bottom electrode and positioned in the inter-metal dielectric. The resistance switching assembly has a reverse T-shape cross-section. The top electrode is disposed on the resistance switching assembly and the inter-metal dielectric.Type: ApplicationFiled: February 27, 2020Publication date: September 2, 2021Applicant: Winbond Electronics Corp.Inventors: Chih-Yao LIN, Po-Yen HSU, Bo-Lun WU
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Publication number: 20200045000Abstract: A notification system capable of attaching pictures includes an editing device, a server, and multiple receiving devices. The editing device includes a data input module for inputting notification editing information. The notification editing information includes at least a picture datum and at least a URL link datum. The server is communicatively connected to the editing device for receiving the notification editing information. The server includes an insert module provided for receiving the notification editing information and inserting the notification editing information into notification information. The receiving device is communicatively connected to the server and includes a receiving module and a display module. The receiving module is provided for receiving the notification information, and the display module is provided for displaying the notification information.Type: ApplicationFiled: August 1, 2019Publication date: February 6, 2020Applicant: AVIVID INNOVATIVE MEDIA CO., LTDInventor: CHIH-YAO LIN
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Publication number: 20180232783Abstract: A web-push notification advertising network system comprises a plurality of secondary servers, a plurality of receiving ends, a plurality of push-notification ends and a main server. Each of the secondary servers has a different domain name, and further includes a push-notification function module. Each of the receiving ends is connected to at least one of the secondary servers. Each of the secondary servers is connected to at least one of the push-notification ends; and the main server includes a database. The database stores user information of all the receiving ends. wherein, the push-notification end sends a push notification message to the corresponding receiving end by the push-notification function module through the secondary server. The secondary server sends to the push notification message to the non-corresponding receiving ends through the main server. Then, the push notification message is sent to other receiving ends via the other secondary servers.Type: ApplicationFiled: July 13, 2017Publication date: August 16, 2018Inventors: Chih Yao Lin, Tzu-Ming Lin, Chia-Hung Tsou, Wei-Kuang Lai
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Patent number: 9685408Abstract: A contact pad structure includes alternately stacked N insulating layers (N?6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions.Type: GrantFiled: November 28, 2016Date of Patent: June 20, 2017Assignee: MACRONIX International Co., Ltd.Inventors: Yu-Wei Jiang, Teng-Hao Yeh, Chia-Jung Chiou, Chih-Yao Lin
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Patent number: 9508645Abstract: A contact pad structure includes alternately stacked N insulating layers (N?6) and N conductive layers, and has N regions arranged in a 2D array exposing the respective conductive layers. When the conductive layers are numbered as first to N-th from bottom to top, the number (Ln) of exposed conductive layer decreases in a column direction in the regions of any row, the difference in Ln is fixed between two neighboring rows of regions, Ln decreases from the two ends toward the center in the regions of any column, and the difference in Ln is fixed between two neighboring columns of regions.Type: GrantFiled: April 14, 2016Date of Patent: November 29, 2016Assignee: MACRONIX International Co., Ltd.Inventor: Chih-Yao Lin