Abstract: A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.

Abstract: A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.

Abstract: A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.

Abstract: A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers which store respective command indexes related to the channel controllers. The BIST controller receives notification from at least two channel controllers of the channel controllers, which indicates that the at least two channel controllers complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least a channel controller from the at least two channel controllers which send the notification, and sends respective next test command(s) to the selected at least one channel controller based on the respective command index(es) of the selected at least one channel controller.

Abstract: A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.

Abstract: A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers which store respective command indexes related to the channel controllers. The BIST controller receives notification from at least two channel controllers of the channel controllers, which indicates that the at least two channel controllers complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least a channel controller from the at least two channel controllers which send the notification, and sends respective next test command(s) to the selected at least one channel controller based on the respective command index(es) of the selected at least one channel controller.

Abstract: A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, ? data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<?<M.

Abstract: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.

Abstract: A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, p data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<?<M.

Abstract: A hybrid error correction method and a memory repair apparatus thereof are provided for a dynamic random access memory (DRAM). The memory repair apparatus includes a mode register and a hybrid error correction code and redundancy (HEAR) module. When the DRAM enters a standby mode, the mode register switches the DRAM to be controlled by the HEAR module. The HEAR module generates parity data of the error correction code within a default refresh period. The HEAR module extends the refresh period of the DRAM and uses the parity data for error detection to locate a data retention error in the DRAM until the maximum allowable refresh period supported by the HEAR module is reached. Before the DRAM returns to a working mode from a standby mode, the HEAR module performs an error correction process according to fail bit data and writes corrected data into the DRAM.

Abstract: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.

Abstract: A test access control apparatus includes test access mechanism (TAM) buses and an extended IEEE 1149.1 Test Access Port (TAP) Controller. The TAM buses support memory built-in-self-test (BIST) circuit for the memory known-good-die (KGD) test, scan chains for the logic KGD test; and through-silicon-via (TSV) chains that are configured to conduct the TSV test that verifies any defect in vertical interconnects between any two chip layers of the stacked chip device. The TAP Controller is coupled to the TAM buses and is configured to control the memory KGD test, the logic KGD test and the TSV test between two chip layers. A cost-effective connection or configuration of test access control apparatus in 3D-IC is also present.