Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: This invention presents a novel method to form uniform or heterogeneous, straight or curved and size-controllable nanostructures including, for example, nanotubes, nanowires, nanoribbons, and nanotapes, including SiNW, using a nanochannel template. In the case of semiconductor nanowires, doping can be included during growth. Electrode contacts are present as needed and may be built in to the template structure. Thus completed devices such as diodes, transistors, solar cells, sensors, and transducers are fabricated, contacted, and arrayed as nanowire or nanotape fabrication is completed. Optionally, the template is not removed and may become part of the structure. Nanodevices such as nanotweezers, nanocantilevers, and nanobridges are formed utilizing the processes of the invention.

Abstract: This invention presents a novel method to form uniform or heterogeneous, straight or curved and size-controllable nanostructures including, for example, nanotubes, nanowires, nanoribbons, and nanotapes, including SiNW, using a nanochannel template. In the case of semiconductor nanowires, doping can be included during growth. Electrode contacts are present as needed and may be built in to the template structure. Thus completed devices such as diodes, transistors, solar cells, sensors, and transducers are fabricated, contacted, and arrayed as nanowire or nanotape fabrication is completed. Optionally, the template is not removed and may become part of the structure. Nanodevices such as nanotweezers, nanocantilevers, and nanobridges are formed utilizing the processes of the invention.

Abstract: This invention presents a novel method to form uniform or heterogeneous, straight or curved and size-controllable nanostructures, nanowires, and nanotapes, including SiNW, in a nanochannel template. In the case of semiconductor nanowires, doping can be included during growth. Electrode contacts are present as needed and built in to the template structure. Thus completed devices such as diodes, transistors, solar cells, sensors, and transducers are fabricated, contacted, and arrayed as nanowire or nanotape fabrication is completed. Optionally, the template is not removed may become part of the structure. Nanostructures such as nanotweezers, nanocantiliver, and nanobridges are formed utilizing the processes of the invention.

Abstract: The invention relates to chemical reactor templates having channel-like voids parallel to the template's major axis. The channel-like voids may have either micro-scale or nano-scale cross sectional areas. The chemical reactor templates may be used to produce micro- and nano-scale filaments and particles which have a variety of uses. In some embodiments a chemical reactor template of the invention have at least two intersecting channel-like voids substantially parallel to the major axis of said template. The invention also relates to methods for manufacturing a chemical reactor template using sacrificial layers. The chemical reactor templates of the invention may be fabricated to have multiple arrays of channel-like structures as well as vertical elements to provide access to act as contacts for the channel-like voids and materials formed within the template. The invention relates to methods for producing filaments and particles using a chemical reactor template.