Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.

Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.

Abstract: A display device includes a flexible substrate, a bonding pad, a light-emitting diode, an encapsulant, and a support structure. The bonding pad and the light-emitting diode are located on the flexible substrate. The encapsulant covers the light-emitting diode. The support structure is laterally located between the light-emitting diode and the bonding pad. The support structure has an inclined surface, and a thickness of the support structure close to the light-emitting diode is greater than the thickness of the support structure close to the bonding pad.

Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.

Abstract: A method of manufacturing a display device includes the following steps. A bonding pad is formed on a dielectric layer. A light-shielding material is formed on the dielectric layer. A temperature of the light-shielding material is increased such that the light-shielding material is cured into a light-shielding layer. During curing the light-shielding material into the light-shielding layer, the light-shielding material flows to and contacts a portion of a surface of the bonding pad. A light-emitting element is electrically connected to the bonding pad.

Abstract: A method of manufacturing a display device includes the following steps. A bonding pad is formed on a dielectric layer. A light-shielding material is formed on the dielectric layer. A temperature of the light-shielding material is increased such that the light-shielding material is cured into a light-shielding layer. During curing the light-shielding material into the light-shielding layer, the light-shielding material flows to and contacts a portion of a surface of the bonding pad. A light-emitting element is electrically connected to the bonding pad.

Abstract: A thin film transistor includes a substrate, a gate electrode disposed on the substrate, a channel layer located on the gate electrode, a gate insulation layer disposed between the gate electrode and the channel layer, an etching stop layer disposed on the channel layer, and a source electrode and a drain electrode disposed on the etching stop layer. The gate electrode has multiple through holes, the etching stop layer has multiple contact holes overlapped with the through holes in a direction perpendicular to the substrate, and the source and drain electrodes are respectively electrically connected to the channel layer through the contact holes. A method of manufacturing the thin film transistor, where the contact holes in the etching stop layer are formed by backside exposure using the gate electrode as a mask. A conductivity of a region of the channel layer exposed by the contact holes has a great conductivity.

Abstract: A thin film transistor includes a substrate, a gate electrode disposed on the substrate, a channel layer located on the gate electrode, a gate insulation layer disposed between the gate electrode and the channel layer, an etching stop layer disposed on the channel layer, and a source electrode and a drain electrode disposed on the etching stop layer. The gate electrode has multiple through holes, the etching stop layer has multiple contact holes overlapped with the through holes in a direction perpendicular to the substrate, and the source and drain electrodes are respectively electrically connected to the channel layer through the contact holes. A method of manufacturing the thin film transistor, where the contact holes in the etching stop layer are formed by backside exposure using the gate electrode as a mask. A conductivity of a region of the channel layer exposed by the contact holes has a great conductivity.

Abstract: A thin film transistor (TFT) array substrate includes a first substrate, a plurality of TFTs formed on the first substrate, a color filter layer covered on the TFTs, and a plurality of pixel electrodes corresponding to the TFTs. The color filter layer is directly formed on the TFTs. The color filter layer includes a plurality of photoresist units. Each of the pixel electrodes is to electrically connected to a drain of the TFT via an opening.

Abstract: A thin film transistor (TFT) array substrate includes a first substrate, a plurality of TFTs formed on the first substrate, a color filter layer covered on the TFTs, and a plurality of pixel electrodes corresponding to the TFTs. The color filter layer is directly formed on the TFTs. The color filter layer includes a plurality of photoresist units. Each of the pixel electrodes is to electrically connected to a drain of the TFT via an opening.

Abstract: A shielding shell includes a frame having a ring-shaped bracket with a receiving chamber therein. The bracket is erected on a printed circuit board with electronic components located in the receiving chamber. A top periphery of the bracket bends inward to form a support eave. At least three restricting portions of inverted-L shape protrude upward and inward at a rear and two symmetrical sides of the top periphery of the bracket respectively. An inserting slot is formed between the restricting portion and the support eave. A cover has a cover plate movably located on the support eave through a front of the frame and further pushed rearward to be inserted in the inserting slots so as to removably cover up the receiving chamber.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (?-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the ?-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the ?-Si layer, wherein interface defects existing between the ?-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (?-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the ?-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the ?-Si layer, wherein interface defects existing between the ?-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: A multimedia communication system includes: an intercom device operable for picking up audio information, and for performing encoding and modulation processes upon the audio information so as to generate a modulated signal; and a multimedia device coupled to the intercom device for receiving the modulated signal therefrom, and operable for performing demodulation and decoding processes upon the modulated signal so as to generate a decoded audio signal, for generating an output audio signal from external audio information contained in an external input signal when the decoded audio signal is not received thereby, for generating the output audio signal from at least the decoded audio signal when the decoded audio signal and the external input signal are received thereby, and for audible reproduction of the output audio signal.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: A method for fabricating polysilicon film is disclosed. First, a first substrate is provided, wherein a plurality of sunken patterns has been formed on the front surface of the first substrate. Then, a second substrate is provided and an amorphous polysilicon film is formed on the second substrate. Next, the amorphous polysilicon film formed on the second substrate is in contact with the front surface of the first substrate. The amorphous polysilicon film is transferred into a polysilicon film by performing an annealing process. Then, the first substrate and the second substrate are separated from each other. This method reduces the cost and the time for fabricating polysilicon film.

Abstract: Manufacturing methods of using a metal imprint technique for growing carbon nanotubes on selective areas and the structures formed thereof are provided. One of the manufacturing methods includes steps of forming a first substrate with tapered structures applied with a metal catalyst, imprinting a second substrate on the first substrate for being a growth substrate, and growing carbon nanotubes on the growth substrate. The other manufacturing method includes steps of forming a first substrate with tapered structures, imprinting the first substrate on a second substrate applied with a metal catalyst for forming a second growth substrate, and growing carbon nanotubes on the second grown substrate. And, the formed structures of the present invention include a substrate, plural carbon nanotubes, and plural imprinted vestiges.

Abstract: A manufacturing method of a semiconductor device, includes the following steps: providing a substrate with an insulated surface; forming an amorphous silicon layer on the insulated surface; imposing a catalytic metal element on the amorphous silicon layer; heating and catalyzing the amorphous silicon layer to form a poly-silicon layer; forming a diffusion layer and a gettering material layer on the poly-silicon layer in order; proceeding an annealing process on the gettering material layer and the poly-silicon layer to move the residual metal catalyst element from the poly-silicon layer toward the gettering material layer due to the concentration gradient; and removing the diffusion layer and the gettering material layer.