Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

Abstract: The present invention provides a method of dynamic thermal management applied to a portable device, wherein the method includes the steps of: obtaining a surface temperature of the portable device; obtaining a junction temperature of a chip of the portable device; and calculating an upper limit of the junction temperature according to the junction temperature and the surface temperature.

Abstract: Dry nano-sizing equipment with fluid mobility effect dryly processes viewable fine-grained substances into a nano-sized dimension by high-pressure airflow resulted from a pressure-generating unit, as well as high-speed fluid and high mechanical momentum generated in a pressure cylinder by high-speed rotation of a booster impeller.

Abstract: The present invention provides a method of dynamic thermal management applied to a portable device, wherein the method includes the steps of: obtaining a surface temperature of the portable device; obtaining a junction temperature of a chip of the portable device; and calculating an upper limit of the junction temperature according to the junction temperature and the surface temperature.

Abstract: Dry nano-sizing equipment with fluid mobility effect dryly processes viewable fine-grained substances into a nano-sized dimension by high-pressure airflow resulted from a pressure-generating unit, as well as high-speed fluid and high mechanical momentum generated in a pressure cylinder by high-speed rotation of a booster impeller.

Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.

Abstract: A power management method for an electronic apparatus is provided. The electronic apparatus includes a plurality of heat sources. The power management method includes the following steps: detecting a temperature of the electronic apparatus; detecting a power of the electronic apparatus; identifying an operating scenario of the electronic apparatus; and referring to the detected temperature, the detected power and the operating scenario to determine whether to allocate a power budget between the heat sources.

Abstract: Techniques pertaining to thermal management for smooth variation in display frame rate are described. A method may involve performing either or both of: (1) determining whether a temperature of at least one portion of an electronic apparatus exceeds a temperature threshold; and (2) determining whether a variation in a frame rate of images displayed on a display device associated with the electronic apparatus exceeds a variation threshold. The method may also involve controlling the frame rate in response to either or both of a first determination that the monitored temperature exceeds the temperature threshold and a second determination that the variation in the frame rate exceeds the variation threshold.

Abstract: A mobile device performs thermal management during concurrent battery charging and workload execution based on a thermal headroom. The thermal headroom is an amount of power, in a form of heat, that heat dissipation hardware in the mobile device is estimated to dissipate when the mobile device operates at a target temperature. After the thermal headroom is determined, the mobile device determines a first power allocation to system loading, which is caused by one or more applications running on the mobile device. The first power allocation is subtracted from the thermal headroom to obtain a second power allocation to a charger, which charges a battery module of the mobile device while the one or more application are running. The mobile device then sets an input power limit of the charger based on the second power allocation.

Abstract: A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.

Abstract: Techniques pertaining to thermal management for smooth variation in display frame rate are described. A method may involve performing either or both of: (1) determining whether a temperature of at least one portion of an electronic apparatus exceeds a temperature threshold; and (2) determining whether a variation in a frame rate of images displayed on a display device associated with the electronic apparatus exceeds a variation threshold. The method may also involve controlling the frame rate in response to either or both of a first determination that the monitored temperature exceeds the temperature threshold and a second determination that the variation in the frame rate exceeds the variation threshold.

Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.

Abstract: A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.

Abstract: A crank puller includes a nut portion having a front end for screwing into a threaded hole on a crank, and an internally threaded bore; a bolt portion screwed through the threaded bore and having a front conical-bottomed hole; a head portion fitted in the conical-bottomed hole and having a front end with an annular groove for receiving an elastic element therein; and a cap portion assembled around the front end of the head portion for pressing against a crank axle, and being replaceable corresponding to a diametrical size of the crank axle.

Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Abstract: A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.

Abstract: A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.