Patents by Inventor Chihiro Arai
Chihiro Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240130410Abstract: An emulsified composition containing methyl cellulose, a starch material, edible oil or fat, and an emulsifying material, in which the emulsifying material contains protein, and the starch material is one or two kinds selected from the group consisting of a component (A) and a component (B) below. component (A): a powdery material satisfying the following conditions (1) to (4), (1) a starch content is equal to or more than 75% by mass, (2) a low molecular weight starch (a peak molecular weight of equal to or more than 3×103 and equal to or less than 5×104) having an amylose content of equal to or more than 5% by mass is included, a content of the low molecular weight starch being equal to or more than 3% by mass and equal to or less than 45% by mass, (3) a degree of swelling in cold water at 25° C. is equal to or more than 5 and equal to or less than 20, and (4) a content under a sieve with openings of 3.35 mm and on a sieve with openings of 0.Type: ApplicationFiled: February 25, 2022Publication date: April 25, 2024Inventors: Koji SAGARA, Junko ARAI, Chihiro ISHIKAWA
-
Publication number: 20240088381Abstract: A positive electrode mixture containing a polyvinylidene fluoride (A); a fluorine-containing copolymer (B) containing vinylidene fluoride unit and tetrafluoroethylene unit; a positive electrode active material (C) represented by the general formula (C): LiyNi1-xMxO2, wherein x is 0.01?x?0.7, y is 0.9?y?2.0, and M represents a metal atom (excluding Li and Ni); and an additive (D). Also disclosed is a positive electrode formed from the positive electrode mixture and a secondary battery including the positive electrode.Type: ApplicationFiled: November 7, 2023Publication date: March 14, 2024Applicant: DAIKIN INDUSTRIES, LTD.Inventors: Yuma ICHINOSE, Shigeaki YAMAZAKI, Chihiro HOSODA, Kanako ARAI, Toshiharu SHIMOOKA
-
Publication number: 20240079595Abstract: A positive electrode mixture containing: a polyvinylidene fluoride (A); a positive electrode active material (C) represented by the general formula (C): LiyNi1-XMxO2, wherein x is 0.01?x?0.7, y is 0.9?y?2.0, and M represents a metal atom (excluding Li and Ni); and an additive (D), wherein the polyvinylidene fluoride (A) is a combination of: (A2) a polymer containing vinylidene fluoride unit and a fluorinated monomer unit; and at least one selected from the group consisting of (A3) a polymer containing vinylidene fluoride unit and a polar group-containing monomer unit, and (A4) a polymer containing vinylidene fluoride unit, a fluorinated monomer unit, and a polar group-containing monomer unit. Also disclosed is a positive electrode famed from the positive electrode mixture and a secondary battery including the positive electrode.Type: ApplicationFiled: November 2, 2023Publication date: March 7, 2024Applicant: DAIKIN INDUSTRIES, LTD.Inventors: Yuma ICHINOSE, Shigeaki YAMAZAKI, Chihiro HOSODA, Kanako ARAI, Toshiharu SHIMOOKA
-
Publication number: 20240014239Abstract: To provide an imaging apparatus that is advantageous for reducing the influence of stray light on a captured image. The imaging apparatus includes: a semiconductor substrate including a plurality of effective pixels that performs photoelectric conversion; an effective covering part including an optical element and covering the plurality of effective pixels in the semiconductor substrate; and a peripheral covering part covering a portion positioned outside the plurality of effective pixels in the semiconductor substrate, in which the plurality of effective pixels and the effective covering part are included in an effective pixel region structure, the portion positioned outside the plurality of effective pixels in the semiconductor substrate and the peripheral covering part are included in a peripheral region structure, and the peripheral region structure includes a recessed interface forming body having a recessed interface.Type: ApplicationFiled: November 12, 2021Publication date: January 11, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Chihiro ARAI, Tomoyoshi FUJINOHARA
-
Publication number: 20230230986Abstract: A solid-state imaging element according to the present disclosure includes a first light receiving pixel, a second light receiving pixel, and a metal layer. The first light receiving pixel receives visible light. The second light receiving pixel receives infrared light. The metal layer is provided to face at least one of a photoelectric conversion unit of the first light receiving pixel and a photoelectric conversion unit of the second light receiving pixel on an opposite side of a light incident side, and contains tungsten as a main component.Type: ApplicationFiled: April 14, 2021Publication date: July 20, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Kazuyoshi YAMASHITA, Shinichiro KURIHARA, Syogo KUROGI, Yusuke UESAKA, Toshiki SAKAMOTO, Hiroyuki KAWANO, Masatoshi IWAMOTO, Takashi TERADA, Sintaro NAKAJIKI, Shinta KOBAYASHI, Chihiro ARAI
-
Patent number: 10748947Abstract: The present disclosure relates to an imaging device, a manufacturing method, and an electronic apparatus. An imaging device includes: a sensor substrate with an effective pixel area; a transparent sealing member that seals a surface of the sensor substrate; a sealing resin that bonds the sensor substrate and the sealing member; and a reinforcing resin that bonds the sensor substrate and the sealing member. A product of adhesive strength per unit area of the sealing resin and the reinforcing resin in the outer peripheral region and an area of a part bonded in the outer peripheral region is set to be larger than a product of adhesive strength per unit area of the sealing resin in the effective pixel area and an area of a part bonded in the effective pixel area. The present technology can be applied to, for example, a CMOS image sensor of WCSP.Type: GrantFiled: July 25, 2017Date of Patent: August 18, 2020Assignee: Sony Semiconductor Solutions CorporationInventors: Yoshiaki Masuda, Atsuhiro Ando, Norihiro Kubo, Chihiro Arai, Sotetsu Saito, Masahiro Tada, Shinji Miyazawa
-
Publication number: 20190172863Abstract: The present disclosure relates to an imaging device, a manufacturing method, and an electronic apparatus—An imaging device includes: a sensor substrate with an effective pixel area; a transparent sealing member that seals a surface of the sensor substrate; a sealing resin that bonds the sensor substrate and the sealing member; and a reinforcing resin that bonds the sensor substrate and the sealing member. A product of adhesive strength per unit area of the sealing resin and the reinforcing resin in the outer peripheral region and an area of a part bonded in the outer peripheral region is set to be larger than a product of adhesive strength per unit area of the sealing resin in the effective pixel area and an area of a part bonded in the effective pixel area. The present technology can be applied to, for example, a CMOS image sensor of WCSP.Type: ApplicationFiled: July 25, 2017Publication date: June 6, 2019Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Atsuhiro ANDO, Norihiro KUBO, Chihiro ARAI, Sotetsu SAITO, Masahiro TADA, Shinji MIYAZAWA
-
Publication number: 20170234971Abstract: In a phase calibration device, a first integrated circuit outputs a transmission signal for generating a transmission wave of a first transmission antenna, a second integrated circuit outputs a transmission signal for generating a transmission wave of a second transmission antenna, a calibration reception antenna is disposed in a state to be theoretically identical in electric coupling amount when receiving the transmission waves of the first transmission antenna and the second transmission antenna, a reception circuit acquires a received signal from the calibration reception antenna, and a control circuit calibrates phases of the transmission signals based on an amplitude of the received signal of the reception circuit when the first integrated circuit and the second integrated circuit output the transmission signals to the first transmission antenna and the second transmission antenna.Type: ApplicationFiled: January 17, 2017Publication date: August 17, 2017Inventor: Chihiro ARAI
-
Patent number: 9094021Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.Type: GrantFiled: March 3, 2013Date of Patent: July 28, 2015Assignee: Renesas Electronics CorporationInventors: Chihiro Arai, Toshiya Uozumi, Keisuke Ueda
-
Patent number: 8963593Abstract: A high-frequency signal processing device having a frequency synthesizer (PLL: Phase Locked Loop) is provided. A control circuit measures oscillation frequencies obtained upon setting a bias current of an oscillation circuit to first and second bias setting values and acquires a frequency difference amount of the oscillation frequencies. The frequency difference amount may be acquired as difference amount of setting values of a coarse adjustment capacitance setting signal (CTRM) using, for example, an automatic frequency selector unit. The control circuit retains a relationship of a difference amount of bias setting values and a difference value of setting values of the CTRM and approximating the relationship to a linear function. Thereafter, the control circuit defines, upon switching the bias current during locking of the PLL, the CTRM based on the linear function and switches the CTRM together with the bias current.Type: GrantFiled: March 18, 2014Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Chihiro Arai, Toshiya Uozumi, Keisuke Ueda
-
Publication number: 20140266342Abstract: A high-frequency signal processing device having a frequency synthesizer (PLL: Phase Locked Loop) is provided. A control circuit measures oscillation frequencies obtained upon setting a bias current of an oscillation circuit to first and second bias setting values and acquires a frequency difference amount of the oscillation frequencies. The frequency difference amount may be acquired as difference amount of setting values of a coarse adjustment capacitance setting signal (CTRM) using, for example, an automatic frequency selector unit. The control circuit retains a relationship of a difference amount of bias setting values and a difference value of setting values of the CTRM and approximating the relationship to a linear function. Thereafter, the control circuit defines, upon switching the bias current during locking of the PLL, the CTRM based on the linear function and switches the CTRM together with the bias current.Type: ApplicationFiled: March 18, 2014Publication date: September 18, 2014Applicant: Renesas Electronics CorporationInventors: Chihiro ARAI, Toshiya UOZUMI, Keisuke UEDA
-
Patent number: 8716811Abstract: A semiconductor device includes a first conduction-type semiconductor substrate, a first semiconductor region of a first conduction-type formed on the semiconductor substrate, a second semiconductor region of a second conduction-type formed on a surface of the first semiconductor region, a third semiconductor region of the second conduction-type formed to be separated from the second semiconductor region on the surface of the first semiconductor region, a fourth semiconductor region of the second conduction-type formed to be separated from the second semiconductor region and the third semiconductor region on the surface of the first semiconductor region, and a first electrode connected to the second semiconductor region and the third semiconductor region.Type: GrantFiled: March 2, 2012Date of Patent: May 6, 2014Assignee: Sony CorporationInventors: Hideki Mori, Chihiro Arai
-
Publication number: 20130257547Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.Type: ApplicationFiled: March 3, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Chihiro Arai, Toshiya Uozumi, Keisuke Ueda
-
Publication number: 20120248541Abstract: A semiconductor device includes a first conduction-type semiconductor substrate, a first semiconductor region of a first conduction-type formed on the semiconductor substrate, a second semiconductor region of a second conduction-type formed on a surface of the first semiconductor region, a third semiconductor region of the second conduction-type formed to be separated from the second semiconductor region on the surface of the first semiconductor region, a fourth semiconductor region of the second conduction-type formed to be separated from the second semiconductor region and the third semiconductor region on the surface of the first semiconductor region, and a first electrode connected to the second semiconductor region and the third semiconductor region.Type: ApplicationFiled: March 2, 2012Publication date: October 4, 2012Applicant: SONY CORPORATIONInventors: Hideki Mori, Chihiro Arai
-
Patent number: 7928511Abstract: A semiconductor device (1) includes a plurality of photodiodes (20) on a semiconductor substrate (11). Cathodes (22) and a common anode (21) of the plurality of photodiodes (20 (20a, 20b)) are formed so as to be electrically independent from the semiconductor substrate (11), the plurality of photodiodes (20) have the common anode (21) and the plurality of separate cathodes (22), and an output of the common anode (21) is considered to be equivalent to a sum of outputs of the plurality of separate photodiodes (20). Alternatively, the plurality of photodiodes have a common cathode and a plurality of separate anodes, and an output of the common cathode is considered to be equivalent to a sum of outputs of a plurality of separate photodiodes. By completely electrically isolating the anode and the cathode of the photodiodes from the substrate, the noise characteristic can be reduced, and crosstalk can be reduced.Type: GrantFiled: August 10, 2006Date of Patent: April 19, 2011Assignee: Sony CorporationInventor: Chihiro Arai
-
Publication number: 20100155867Abstract: A semiconductor device (1) includes a plurality of photodiodes (20) on a semiconductor substrate (11). Cathodes (22) and a common anode (21) of the plurality of photodiodes (20 (20a, 20b)) are formed so as to be electrically independent from the semiconductor substrate (11), the plurality of photodiodes (20) have the common anode (21) and the plurality of separate cathodes (22), and an output of the common anode (21) is considered to be equivalent to a sum of outputs of the plurality of separate photodiodes (20). Alternatively, the plurality of photodiodes have a common cathode and a plurality of separate anodes, and an output of the common cathode is considered to be equivalent to a sum of outputs of a plurality of separate photodiodes. By completely electrically isolating the anode and the cathode of the photodiodes from the substrate, the noise characteristic can be reduced, and crosstalk can be reduced.Type: ApplicationFiled: August 10, 2006Publication date: June 24, 2010Applicant: SONY CORPORATIONInventor: Chihiro Arai
-
Patent number: 7675143Abstract: A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.Type: GrantFiled: October 29, 2007Date of Patent: March 9, 2010Assignee: Sony CorporationInventors: Takahide Kadoyama, Masayoshi Abe, Atsushi Kamo, Takaaki Yamada, Chihiro Arai
-
Publication number: 20080099886Abstract: A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.Type: ApplicationFiled: October 29, 2007Publication date: May 1, 2008Applicant: Sony CorporationInventors: Takahide Kadoyama, Masayoshi Abe, Atsushi Kamo, Takaaki Yamada, Chihiro Arai
-
Patent number: 7271046Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.Type: GrantFiled: December 15, 2005Date of Patent: September 18, 2007Assignee: Sony CorporationInventor: Chihiro Arai
-
Patent number: 7064417Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.Type: GrantFiled: May 15, 2002Date of Patent: June 20, 2006Assignee: Sony CorporationInventor: Chihiro Arai