Abstract: A semiconductor device includes a semiconductor substrate in which an effective region through which a current flows and a termination region formed so as to surround an outer peripheral side of the effective region are defined, an oxide film provided in contact with an upper surface of the termination region so as to cover the upper surface, an organic insulating film containing an insulating material and provided so as to cover a portion of the oxide film excluding the peripheral portion, and at least one of a groove concave downward and a ridge protruding upward in the portion of the oxide film covered with the organic insulating film, in which the groove has a portion in which a width thereof decreases upward, and the ridge has a portion in which the width thereof increases upward.

Abstract: Provided is a method of manufacturing a silicon carbide semiconductor device that suppresses the crawling up of a bonding material to the side surfaces of a chip, thereby suppressing a decrease in productivity. In the method of manufacturing the silicon carbide semiconductor device, the method includes, preparing a semiconductor wafer, forming semiconductor elements on the semiconductor wafer, forming a trench, which has a bottom having a roundness, on one main surface of the semiconductor wafer, and performing dicing at a position of the trench having the bottom having the roundness thereby separating the semiconductor elements into individual pieces.

Abstract: Polysilicon films (P1,P2) are simultaneously formed on a wafer (W1) and a monitor wafer (W2) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P2) formed on the monitor wafer (W2) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P1) formed on the wafer (W1) is etched using the selected mask pattern to form the polysilicon resistor (5).

Abstract: A silicon carbide substrate is provided with a first surface and a second surface opposite the first surface. The silicon carbide substrate includes an n-type region connecting the first surface and the second surface, and a p-type region being in contact with the first surface and connecting the first surface and the second surface. A first anode electrode is Schottky-joined, on the first surface, to the n-type region. A first cathode electrode is ohmically joined, on the second surface, to the n-type region. A second anode electrode is ohmically joined, on the first surface, to the p-type region. A second cathode electrode is Schottky-joined, on the second surface, to the p-type region.

Abstract: Polysilicon films (P1,P2) are simultaneously formed on a wafer (W1) and a monitor wafer (W2) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P2) formed on the monitor wafer (W2) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P1) formed on the wafer (W1) is etched using the selected mask pattern to form the polysilicon resistor (5).

Abstract: A silicon carbide substrate is provided with a first surface and a second surface opposite the first surface. The silicon carbide substrate includes an n-type region connecting the first surface and the second surface, and a p-type region being in contact with the first surface and connecting the first surface and the second surface. A first anode electrode is Schottky-joined, on the first surface, to the n-type region. A first cathode electrode is ohmically joined, on the second surface, to the n-type region. A second anode electrode is ohmically joined, on the first surface, to the p-type region. A second cathode electrode is Schottky-joined, on the second surface, to the p-type region.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface of the silicon carbide semiconductor layer; a Schottky electrode formed on the surface of the silicon carbide semiconductor layer on an inner periphery side relative to the field insulating film, the Schottky electrode being formed to overlap onto the field insulating film; a front-surface electrode that covers the Schottky electrode and extends on the field insulating film beyond a peripheral edge of the Schottky electrode; and a terminal well region of a second conductivity type that is formed to be in contact with a part of the Schottky electrode in an upper part of the silicon carbide semiconductor layer and extends in the silicon carbide semiconductor layer on an outer periphery side relative to a peripheral edge of the front-surface electrode.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface of the silicon carbide semiconductor layer; a Schottky electrode formed on the surface of the silicon carbide semiconductor layer on an inner periphery side relative to the field insulating film, the Schottky electrode being formed to overlap onto the field insulating film; a front-surface electrode that covers the Schottky electrode and extends on the field insulating film beyond a peripheral edge of the Schottky electrode; and a terminal well region of a second conductivity type that is formed to be in contact with a part of the Schottky electrode in an upper part of the silicon carbide semiconductor layer and extends in the silicon carbide semiconductor layer on an outer periphery side relative to a peripheral edge of the front-surface electrode.

Abstract: A semiconductor device includes a transistor, a first diode, and a second diode. A collector of the transistor and a cathode of the first diode are electrically connected. The collector of the transistor and a cathode of the second diode are electrically connected, and an emitter of the transistor and an anode of the second diode are electrically connected. The first diode and the second diode are formed in an identical substrate. Thereby, the semiconductor device can be produced in a smaller size and in less steps.

Abstract: A semiconductor device includes a transistor, a first diode, and a second diode. A collector of the transistor and a cathode of the first diode are electrically connected. The collector of the transistor and a cathode of the second diode are electrically connected, and an emitter of the transistor and an anode of the second diode are electrically connected. The first diode and the second diode are formed in an identical substrate. Thereby, the semiconductor device can be produced in a smaller size and in less steps.

Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

Abstract: The gate of an IGBT is connected to a gate terminal. One end of a clamping element is connected to an anode terminal. A voltage higher than a clamping voltage is applied between the gate and the emitter, to thereby test the dielectric breakdown voltage of a gate insulating film of the IGBT. The IGBT is eliminated which has a gate insulating film at a dielectric breakdown voltage failing to fall within its proper distribution range. Thereafter, a gate terminal and an anode terminal are wire bonded in the normal IGBT.

Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

Abstract: The gate of an IGBT is connected to a gate terminal. One end of a clamping element is connected to an anode terminal. A voltage higher than a clamping voltage is applied between the gate and the emitter, to thereby test the dielectric breakdown voltage of a gate insulating film of the IGBT. The IGBT is eliminated which has a gate insulating film at a dielectric breakdown voltage failing to fall within its proper distribution range. Thereafter, a gate terminal and an anode terminal are wire bonded in the normal IGBT.

Abstract: A semiconductor device made of silicon carbide is provided. In the case of a silicon carbide Schottky barrier diode, for example, a p-type region (104) is provided on the side of a cathode electrode (103) serving as an ohmic electrode. The provision of the p-type region allows carriers to be injected from the p-type region in opposition to a reverse current between an anode and the cathode at switch-off and to recombine with carriers carrying the reverse current. That is, a change in the number of carriers is suppressed in an n-type region during a switching operation. This suppresses variations in resistance component and capacitance component. Consequently, the semiconductor device is less prone to oscillations in voltage and current during the switching operation. In the case of a silicon carbide MESFET, the provision of the p-type region on a source electrode side produces similar effects.

Abstract: An n.sup.- layer (2E) having a low impurity concentration is epitaxially grown on a surface (S1) of an n.sup.+ silicon substrate (1) having a high impurity concentration to a depth (D), and phosphorus ions (P) are implanted from the surface (S1) to the inside of the n.sup.- layer (2E). A SiO.sub.2 film is formed on the surface S1 by thermal oxidation, and an opening hole is formed in the SiO.sub.2 film. Using the opening hole, p-type impurities are implanted and diffused by thermal oxidation in the ion-implanted n.sup.- layer (2E), forming a p-type diffusion layer (well) from the surface (S1) to a predetermined depth. In this way, an n layer is formed in place of the n.sup.- layer (2E). The concentration distribution of impurity in the n layer monotonically decreases from the side of the surface (S1) and reaches its minimum on the side of an interface (BS). Then, a predetermined electrode is formed, completing the device.