Patents by Inventor Chihiro Tomita

Chihiro Tomita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162265
    Abstract: A solid-state imaging device includes a first semiconductor layer, a second semiconductor layer, and an external terminal. The first semiconductor layer has a pixel region in which a plurality of pixels is arranged, and a peripheral region provided around the pixel region. The second semiconductor layer is stacked on the first semiconductor layer, and is provided with a pixel circuit coupled to the pixels. The external terminal is provided in an opening that communicates with the second semiconductor layer from the peripheral region in the first semiconductor layer. A first isolator is provided in the first semiconductor layer within the peripheral region, and surrounds at least a portion of an outer periphery of the opening. A second isolator is provided in the second semiconductor layer within a region corresponding to the peripheral region, and surrounds at least a portion of the outer periphery of the opening.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 16, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Chihiro TOMITA, Koichiro ZAITSU, Hidenobu TSUGAWA, Junpei YAMAMOTO
  • Publication number: 20240038815
    Abstract: A light detecting device includes a semiconductor layer having a first surface and a second surface located on opposite sides to each other in a thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first isolation region. The photoelectric conversion cell includes a first photoelectric conversion region adjacent to a second photoelectric conversion region in plan view and each having a photoelectric conversion unit and a transfer transistor, a second isolation region arranged between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in a thickness direction of the semiconductor layer, and an element formation region partitioned on the first surface side of the semiconductor layer by a third isolation region and provided with a pixel transistor. The element formation region extends over the first and second photoelectric conversion regions in plan view.
    Type: Application
    Filed: March 9, 2022
    Publication date: February 1, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hirofumi YAMASHITA, Chihiro TOMITA, Harumi TANAKA
  • Patent number: 11888020
    Abstract: The present disclosure relates to a semiconductor device, a solid-state imaging device, and a method for manufacturing a semiconductor device capable of improving the voltage dependency of a gate capacitance type. Provided is a semiconductor device having a laminated structure in which a compound layer formed on a surface of a semiconductor layer and formed by the semiconductor layer reacting with metal, an insulating film layer in contact with the compound layer, and an electrode layer formed on the insulating film layer are laminated. The present technology can be applied, for example, to an analog-to-digital (AD) conversion part included in the solid-state imaging device.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 30, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Chihiro Tomita, Shintaro Okamoto, Tomohiro Hirai
  • Patent number: 11837668
    Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 5, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Chihiro Tomita, Tomohiro Hirai, Shintaro Okamoto, Kentaro Eda, Takashi Watanabe, Kazuki Yamaguchi, Norikazu Kasahara, Kohei Suzuki
  • Publication number: 20220384561
    Abstract: A resistance element includes a resistive film, in which the resistive film is adjacent to a protrusion formed on a surface of a semiconductor substrate, the protrusion including a step traversed by the resistive film.
    Type: Application
    Filed: August 7, 2020
    Publication date: December 1, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Chihiro TOMITA, Tomohiro HIRAI
  • Publication number: 20220130948
    Abstract: The present disclosure relates to a semiconductor device, a solid-state imaging device, and a method for manufacturing a semiconductor device capable of improving the voltage dependency of a gate capacitance type. Provided is a semiconductor device having a laminated structure in which a compound layer formed on a surface of a semiconductor layer and formed by the semiconductor layer reacting with metal, an insulating film layer in contact with the compound layer, and an electrode layer formed on the insulating film layer are laminated. The present technology can be applied, for example, to an analog-to-digital (AD) conversion part included in the solid-state imaging device.
    Type: Application
    Filed: February 7, 2020
    Publication date: April 28, 2022
    Inventors: CHIHIRO TOMITA, SHINTARO OKAMOTO, TOMOHIRO HIRAI
  • Publication number: 20220052208
    Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.
    Type: Application
    Filed: September 30, 2019
    Publication date: February 17, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Chihiro TOMITA, Tomohiro HIRAI, Shintaro OKAMOTO, Kentaro EDA, Takashi WATANABE, Kazuki YAMAGUCHI, Norikazu KASAHARA, Kohei SUZUKI
  • Patent number: 7903395
    Abstract: An electronic device mounting structure for fitting an ECU (electronic device) in an open space formed in a device mounting housing and for holding the ECU fitted in the open space by a holding finger formed on the device mounting housing, includes a stopper formed in the device mounting housing so as to be juxtaposed with the holding finger, the stopper being configured to prevent the ECU from falling out of the device mounting housing.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: March 8, 2011
    Assignee: Nifco Inc.
    Inventors: Tatsuma Nishida, Hiroshi Ueno, Atsumasa Matsui, Chihiro Tomita, Naohiro Shimajiri, Kazuo Yoshino, Kunio Kiyohara, Hiromasa Tanaka
  • Publication number: 20110008502
    Abstract: The present invention relates to a processed food or beverage composition containing a dextrin having the following characteristics (a) to (d): (a) the dextrin has a blue value within the range of 0.4 to 1.2, (b) having a gel strength of 4 N/cm2 or more as measured after being dissolved in distilled water at 80° C. to prepare a 30 wt % aqueous solution of the dextrin, and then being allowed to stand at 5° C. for 24 hours, (c) having a viscosity of 100 mPa·s or less as measured after being dissolved in distilled water at 25° C. to prepare a 30 wt % aqueous solution of the dextrin, and then being allowed to stand at 25° C. for five minutes; and (d) the ratio (A/B) of the following gel strengths A and B being 2 or less: A: a gel strength (N/cm2) as measured after being dissolved in distilled water at 80° C. to prepare a 30 wt % aqueous solution of the dextrin, and then being allowed to stand at 5° C. for 24 hours, and B: a gel strength (N/cm2) as measured after being dissolved in distilled water at 25° C.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 13, 2011
    Applicant: SAN-EI GEN F.F.I., INC.
    Inventors: Tomohiro Hosomi, Kenshi Mitsunaga, Kazumi Iwai, Chihiro Tomita, Daisaku Ito, Takashi Konda, Kyoko Muramori, Juri Oshita, Chiharu Hirai, Keiko Nagayasu, Satoru Wada, Satoshi Toyoizumi, Yasuyuki Fujita, Kohei Nakajima, Hirokazu Maruoka, Aya Miyawaki
  • Publication number: 20090087537
    Abstract: This invention provides a method of preparing emulsion compositions particularly emulsion foods, with excellent emulsifying activity, emulsion stability, heat resistance, and texture or mouthfeel. The method can be performed by carrying out a step (1) mixing pectin obtained by heating sugar beet pectin derived from sugar beet in powder form at a temperature of 50 to 150° C. at a relative humidity of 20 to 90% for 1 to 48 hours with raw materials for emulsion compositions; and a step (2) emulsifying the mixture obtained in the step (1), or, in place of step (1), (a) homogenizing a modified pectin in alternatively water systems; (b) mixing the water dispersions of the modified pectin obtained in step (a) with raw materials for emulsion compositions; and (c) emulsifying the mixture obtained in step (b). Thus, emulsion compositions can be prepared.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 2, 2009
    Applicants: SAN-EI GEN F.F.I., INC., PHILLIPS HYDROCOLLOIDS RESEARCH LIMITED
    Inventors: Mika Hiroe, Yohei Kataoka, Takahiro Funami, Takashi Konda, Chihiro Tomita, Satoshi Toyoizumi, Tomohiro Hosomi, Sayaka Ishihara
  • Publication number: 20080297993
    Abstract: An electronic device mounting structure for fitting an ECU (electronic device) in an open space formed in a device mounting housing and for holding the ECU fitted in the open space by a holding finger formed on the device mounting housing, includes a stopper formed in the device mounting housing so as to be juxtaposed with the holding finger, the stopper being configured to prevent the ECU from falling out of the device mounting housing.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 4, 2008
    Applicant: NIFCO INC.
    Inventors: Tatsuma Nishida, Hiroshi Ueno, Atsumasa Matsui, Chihiro Tomita, Naohiro Shimajiri, Kazuo Yoshino, Kunio Kiyohara, Hiromasa Tanaka