Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: A support apparatus for holding a monitor is disclosed. The support apparatus can include an elongate arm pivotally connected to a support member and configured to couple to the monitor. The elongate arm can be pivotable within a range of motion between first and second mechanical stops, and can include a locking mechanism to lock the elongate arm into a selected pivoting position. The support member can extend between first and second side walls that define the mechanical stops. The support apparatus can include a mounting mechanism comprising receiving slots for securely holding the monitor. The mounting mechanism can allow the monitor to be mounted at various positions and orientations. The support apparatus allows the monitor to be positioned at various angles and heights, providing flexibility and customization in the placement of the monitor.

Abstract: A mounting system for an electronic device is disclosed. The mounting system includes a mounting plate; a plurality of fasteners for coupling the mounting plate with the electronic device; a single main gear mounted on the mounting plate; a plurality of secondary gears coupled, respectively, to the plurality of fasteners; and a plurality of intermediate gears mounted on the mounting plate and rotationally coupled between the single main gear and the plurality of secondary gears. Rotation of each of the plurality of secondary gears causes a fastening movement of a respective one of the plurality of fasteners. Simultaneous rotation of the plurality of intermediate gears causes the plurality of secondary gears to rotate simultaneously in response to a single rotational force being received by the main gear. The simultaneous rotation of the plurality of intermediate gears causes a simultaneous fastening movement of the plurality of secondary gears.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A device for testing a group of radio-frequency (RF) chip modules and a method for using the same is disclosed. The device includes a signal analyzer, a power divider, control ICs, a signal controller, and a power combiner. The power divider receives an RF signal and transmits RF input signals to the RF chip modules and the control ICs in response to the RF signal. The signal controller controls each control IC to adjust at least one of the power and the phase of the corresponding RF input signal, thereby generating an RF output signal. The power combiner receives the RF output signal from each control IC to generate a test signal. The signal analyzer receives the test signal and obtains RF properties corresponding to at least one of the power and the phase of each RF output signal.

Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a search circuitry and a substitution check circuitry. The key generation circuitry is arranged operably to convert a first value of one byte corresponding to a plaintext, an intermediate encryption result, or a round key into a second value of a K-bit according to an 8-to-K lookup table, where K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity. The substitution check circuitry is arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, where a total amount of the formulae is K minus 8.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.

Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.

Abstract: A light emitting device controls its mixed CCT by the configuration of at least one light emitter, at least one diode and at least two power distribution components. The present disclosure is mainly based on the hardware design of diode and jumper, which effectively replaces the resistors and manual switches of the conventional light emitting device with diodes, wherein the resistors and the manual switches of the conventional light emitting device cause voltage instability and other problems. The present disclosure can achieve the demand for miniaturization of the light emitting device by plugging the jumper into pins, and further can achieve the main advantages of stabilizing the voltage of the overall light emitting device, thereby stabilizing the luminous performance of the overall light emitting device, and emitting the mixed light with the required CCT. The present disclosure also illustrates a lamp assembly using the aforementioned light emitting device.