Patents by Inventor Chika Nishioka

Chika Nishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fault simulator for verifying reliability of test pattern
    Patent number: 7096384
    Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 22, 2006
    Assignees: Renesas Technology Corp., Mitsubishi Electric System LSI Design Corporation
    Inventors: Chika Nishioka, Yoshikazu Akamatsu, Hideyuki Ohtake
  • Fault simulator for verifying reliability of test pattern
    Publication number: 20040088627
    Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.
    Type: Application
    Filed: February 19, 2003
    Publication date: May 6, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha and Mitsubishi Electric System LSI Design Corporation
    Inventors: Chika Nishioka, Yoshikazu Akamatsu, Hideyuki Ohtake