Patents by Inventor Chikako CHIDA

Chikako CHIDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8994183
    Abstract: A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: March 31, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akihisa Iwasaki, Michiya Takahashi, Akira Ueki, Chikako Chida, Dai Motojima
  • Patent number: 8421233
    Abstract: A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length L1 in a direction parallel to a wire width direction of the first wide portion is greater than a length L2 in a direction parallel to a wire length direction of the first wide portion.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: April 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Chikako Chida, Fumito Itou, Hiroshige Hirano
  • Publication number: 20100289151
    Abstract: A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length L1 in a direction parallel to a wire width direction of the first wide portion is greater than a length L2 in a direction parallel to a wire length direction of the first wide portion.
    Type: Application
    Filed: April 2, 2010
    Publication date: November 18, 2010
    Inventors: Chikako CHIDA, Fumito Itou, Hiroshige Hirano