Patents by Inventor Chikayoshi Kamata

Chikayoshi Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8879307
    Abstract: A magnetoresistive device of an embodiment includes: first and second devices each including, a first magnetic layer having a changeable magnetization perpendicular to a film plane, a second magnetic layer having a fixed and perpendicular magnetization, and a nonmagnetic layer interposed between the first and second magnetic layers, the first and second devices being disposed in parallel on a first face of an interconnect layer; and a TMR device including a third magnetic layer having perpendicular magnetic anisotropy and having a changeable magnetization, a fourth magnetic layer having a fixed magnetization parallel to a film plane, and a tunnel barrier layer interposed between the third and fourth magnetic layers, the TMR device being disposed on a second face of the interconnect layer, and the third magnetic layer being magnetostatically coupled to the first magnetic layers of the first and second devices.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Naoharu Shimomura, Hiroaki Yoda, Junichi Ito, Minoru Amano, Chikayoshi Kamata, Keiko Abe
  • Patent number: 8841139
    Abstract: A method of fabricating a magnetic memory according to an embodiment includes: forming a separation layer on a first substrate; sequentially forming a first ferromagnetic layer, a first nonmagnetic layer, and a second ferromagnetic layer on the separation layer, at least one of the first and the second ferromagnetic layers having a single crystal structure; forming a first conductive bonding layer on the second ferromagnetic layer; forming a second conductive bonding layer on a second substrate, on which a transistor and a wiring are formed, the second conductive bonding layer electrically connecting to the transistor; arranging the first and second substrate so that the first conductive bonding layer and the second conductive bonding layer are opposed to each other, and bonding the first and the second conductive bonding layers to each other; and separating the first substrate from the first ferromagnetic layer by using the separation layer.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chikayoshi Kamata, Minoru Amano, Tadaomi Daibou, Junichi Ito
  • Publication number: 20140206106
    Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.
    Type: Application
    Filed: March 24, 2014
    Publication date: July 24, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeki Takahashi, Yuichi Ohsawa, Junichi Ito, Chikayoshi Kamata, Saori Kashiwada, Minoru Amano, Hiroaki Yoda
  • Publication number: 20140131649
    Abstract: According to one embodiment, a magnetoresistance element includes a first magnetic layer having first and second surfaces, a second magnetic layer, an intermediate layer provided between the first surface and the second magnetic layer, a first layer provided on the second surface, containing B and at least one element selected from Hf, Al, Mg, and Ti and having third and fourth surfaces, a second layer provided on the fourth surface and containing B and at least one element selected from Hf, Al, and Mg, and an insulating layer provided on a sidewall of the intermediate layer and containing at least one element selected from the Hf, Al, and Mg contained in the second layer.
    Type: Application
    Filed: September 11, 2013
    Publication date: May 15, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tadaomi DAIBOU, Eiji KITAGAWA, Chikayoshi KAMATA, Saori KASHIWADA, Yushi KATO, Megumi YAKABE
  • Patent number: 8710605
    Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Takahashi, Yuichi Ohsawa, Junichi Ito, Chikayoshi Kamata, Saori Kashiwada, Minoru Amano, Hiroaki Yoda
  • Publication number: 20140087483
    Abstract: According to one embodiment, a manufacturing method of a magnetoresistive effect element includes forming a laminated structure on a substrate, the laminated structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having an invariable magnetization direction, and a non-magnetic layer between the first and second magnetic layers, forming a first mask layer having a predetermined plane shape on the laminated structure, and processing the laminated structure based on the first mask layer by using an ion beam whose solid angle in a center of the substrate is 10° or more.
    Type: Application
    Filed: March 19, 2013
    Publication date: March 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi OHSAWA, Junichi Ito, Saori Kashiwada, Chikayoshi Kamata, Naoki Tamaoki
  • Publication number: 20140084402
    Abstract: According to one embodiment, a magnetic memory includes a first magnetoresistive element includes a storage layer with a perpendicular and variable magnetization, a tunnel barrier layer, and a reference layer with a perpendicular and invariable magnetization, and stacked in order thereof in a first direction, and a first shift corrective layer with a perpendicular and invariable magnetization, the first shift corrective layer and the storage layer arranged in a direction intersecting with the first direction. Magnetization directions of the reference layer and the first shift corrective layer are the same.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoharu SHIMOMURA, Eiji Kitagawa, Chikayoshi Kamata, Minoru Amano, Yuichi Ohsawa, Daisuke Saida, Megumi Yakabe, Hiroaki Maekawa
  • Publication number: 20130307099
    Abstract: According to one embodiment, a magnetic memory element includes a first magnetic layer having a first surface and a second surface being opposite to the first surface, a second magnetic layer, an intermediate layer which is provided between the first surface of the first magnetic layer and the second magnetic layer, a layer which is provided on the second surface of the first magnetic layer, the layer containing B and at least one element selected from Hf, Al, and Mg, and an insulating layer which is provided on a sidewall of the intermediate layer, the insulating layer containing at least one element selected from the Hf, Al, and Mg contained in the layer.
    Type: Application
    Filed: December 28, 2012
    Publication date: November 21, 2013
    Inventors: Eiji KITAGAWA, Chikayoshi Kamata, Saori Kashiwada, Yushi Kato, Tadaomi Daibou
  • Patent number: 8581424
    Abstract: According to one embodiment, an information recording/reproducing device including a semiconductor substrate, a first interconnect layer on the semiconductor substrate, a first memory cell array layer on the first interconnect layer, and a second interconnect layer on the first memory cell array layer. The first memory cell array layer comprises an insulating layer having an alignment mark, and a stacked layer structure on the insulating layer and including a storage layer and an electrode layer. All of the layers in the stacked layer structure comprises a material with a permeability of visible light of 1% or more.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Hirai, Tsukasa Nakai, Kohichi Kubo, Chikayoshi Kamata, Takayuki Tsukamoto, Shinya Aoki
  • Patent number: 8576616
    Abstract: According to one embodiment, a magnetic element includes first and second conductive layers, an intermediate interconnection, and first and second stacked units. The intermediate interconnection is provided between the conductive layers. The first stacked unit is provided between the first conductive layer and the interconnection, and includes first and second ferromagnetic layer and a first nonmagnetic layer provided between the first and second ferromagnetic layers. The second stacked unit is provided between the second conductive layer and the interconnection, and includes third and fourth ferromagnetic layers and a second nonmagnetic layer provided between the third and fourth ferromagnetic layers. A magnetization direction of the second ferromagnetic layer is determined by causing a spin-polarized electron and a magnetic field to act on the second ferromagnetic layer.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Minoru Amano, Junichi Ito, Yuichi Ohsawa, Saori Kashiwada, Chikayoshi Kamata, Tadaomi Daibou
  • Publication number: 20130249028
    Abstract: A method of fabricating a magnetic memory according to an embodiment includes: forming a separation layer on a first substrate; sequentially forming a first ferromagnetic layer, a first nonmagnetic layer, and a second ferromagnetic layer on the separation layer, at least one of the first and the second ferromagnetic layers having a single crystal structure; forming a first conductive bonding layer on the second ferromagnetic layer; forming a second conductive bonding layer on a second substrate, on which a transistor and a wiring are formed, the second conductive bonding layer electrically connecting to the transistor; arranging the first and second substrate so that the first conductive bonding layer and the second conductive bonding layer are opposed to each other, and bonding the first and the second conductive bonding layers to each other; and separating the first substrate from the first ferromagnetic layer by using the separation layer.
    Type: Application
    Filed: September 20, 2012
    Publication date: September 26, 2013
    Inventors: Chikayoshi KAMATA, Minoru Amano, Tadaomi Daibou, Junichi Ito
  • Publication number: 20130248355
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first magnetic layer, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, forming a hard mask layer on the second magnetic layer, and patterning the second magnetic layer, the tunnel barrier layer, and the first magnetic layer, with a cluster ion beam using the hard mask layer as a mask, wherein the cluster ion beam comprises cluster ions, cluster sizes of the cluster ions are distributed, and a peak value of the distribution of the cluster sizes is 2 pieces or more and 1000 pieces or less.
    Type: Application
    Filed: September 18, 2012
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi Ohsawa, Junichi Ito, Shigeki Takahashi, Saori Kashiwada, Chikayoshi Kamata
  • Patent number: 8541766
    Abstract: According to one embodiment, a nonvolatile memory device includes a recording layer and a conductive first layer. The recording layer includes a main group element, a transition element, and oxygen. The recording layer is capable of recording information by changing reversibly between a high resistance state and a low resistance state. The first layer is made of at least one selected from a metal, a metal oxide, a metal nitride, and a metal carbide. The first layer is provided adjacent to the recording layer. The first layer includes the main group element with a concentration lower than a concentration of the main group element of the recording layer.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamaguchi, Chikayoshi Kamata
  • Patent number: 8508979
    Abstract: According to one embodiment, a magnetic recording element includes a stacked body. The stacked body includes a first and a second stacked unit. The first stacked unit includes first and second ferromagnetic layers and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first and second ferromagnetic layers. The second stacked unit is stacked with the first stacked unit and includes third and fourth ferromagnetic layers and a second nonmagnetic layer. The fourth ferromagnetic layer is stacked with the third ferromagnetic layer. The second nonmagnetic layer is provided between the third and fourth ferromagnetic layers. An outer edge of the fourth ferromagnetic layer includes a portion outside an outer edge of the first stacked unit in a plane. A magnetization direction of the second ferromagnetic layer is determined by causing a spin-polarized electron and a rotating magnetic field to act on the second ferromagnetic layer.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 13, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Minoru Amano, Junichi Ito, Yuichi Ohsawa, Saori Kashiwada, Chikayoshi Kamata, Tadaomi Daibou
  • Patent number: 8488375
    Abstract: According to one embodiment, a magnetic recording element includes a stacked body including a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer and a first nonmagnetic layer. Magnetization of the first ferromagnetic layer is substantially fixed in a first direction being perpendicular to a first ferromagnetic layer surface. The second stacked unit includes a third ferromagnetic layer, a fourth ferromagnetic layer and a second nonmagnetic layer. Magnetization of the fourth ferromagnetic layer is substantially fixed in a second direction being perpendicular to a fourth ferromagnetic layer surface. The first direction is opposite to the second direction.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Minoru Amano, Junichi Ito, Yuichi Ohsawa, Saori Kashiwada, Chikayoshi Kamata, Shigeki Takahashi
  • Patent number: 8431210
    Abstract: In one embodiment, there is provided a master for producing a stamper. The master includes: a substrate made of a first material and comprising a first surface, wherein the first surface of the substrate is formed with a groove; a first layer made of a second material and formed in the groove, wherein the second material is different from the first material, and wherein a surface of the first layer is substantially flush with the first surface of substrate; and a projection portion formed on at least one of the first surface of the substrate and the surface of the first layer. The first material is silicon and the second material is selected from silicon oxide, aluminum oxide, titanium oxide, and glass.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Saori Kashiwada, Yuichi Oshawa, Junichi Ito, Chikayoshi Kamata, Yoshiyuki Kamata
  • Patent number: 8431920
    Abstract: According to one embodiment, an information recording and reproducing device includes a recording layer which includes a typical element and a transition element, and stores a state of a first electric resistivity and a state of a second electric resistivity different from the first electric resistivity by a movement of the typical element, and an electrode layer which is disposed at one end of the recording layer to apply a voltage or a current to the recording layer. The recording layer includes a first region which is in contact with the electrode layer and the electrode layer includes a second region which is in contact with the recording layer. The first and second regions are opposite to each other. And the first and second regions include the typical element, and a concentration of the typical element in the second region is higher than that in the first region.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: April 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chikayoshi Kamata, Takayuki Tsukamoto, Takeshi Yamaguchi, Tsukasa Nakai, Takahiro Hirai, Shinya Aoki, Kohichi Kubo
  • Patent number: 8421051
    Abstract: According to one embodiment, a resistance-change memory includes a variable resistance element having a laminated structure in which a first electrode, a resistance-change film and a second electrode are laminated, and set to a low-resistance state and a high-resistance state according to stored data, an insulating film provided on a side surface of the variable resistance element, and a fixed resistance element provided on a side surface of the insulating film, and includes a conductive film, the fixed resistance element being connected in parallel with the variable resistance element.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru Sato, Kohichi Kubo, Chikayoshi Kamata, Noriko Bota
  • Patent number: 8416606
    Abstract: According to one embodiment, an information recording and reproducing device includes a recording layer and a driving unit. The recording layer includes a first layer containing a first compound. The first compound includes a first positive ion element. The first positive ion element is made of a transition metal element and serves as a first positive ion. The second positive ion element serves as a second positive ion. The driving unit is configured to generate a phase change in the recording layer and to record information by at least one of application of a voltage and application of a current to the recording layer. The coordination number of the first positive ion element at a position of a second coordination of the second positive ion element is 80% or more and less than 100% of the coordination number when the first compound is assumed to be a perfect crystal.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: April 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Tsukamoto, Tsukasa Nakai, Chikayoshi Kamata, Mariko Hayashi, Fumihiko Aiga, Takeshi Yamaguchi
  • Patent number: 8391045
    Abstract: An information recording/reproducing device includes a first electrode layer, a second electrode layer, a recording layer as a variable resistance between the first and second electrode layer, and a circuit which supplies a voltage to the recording layer to change a resistance of the recording layer. Each of the first and second electrode layers is comprised of IV or III-V semiconductor doped with p-type carrier or n-type carrier.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kohichi Kubo, Hirofumi Inoue, Mitsuru Sato, Chikayoshi Kamata, Shinya Aoki, Noriko Bota