Abstract: A display device includes a display module and a camera module. The camera module includes a first housing, a second housing and a camera unit. The first housing is movably disposed on the display module. The second housing is separably connected to the first housing. The camera unit is disposed on the second housing. The second housing is able to move with the first housing in relative to the display module, such that the camera unit is exposed from the display module or hidden in the display module. When the second housing is separated from the first housing, the second housing is able to rotate in relative to the first housing, so as to adjust an orientation of the camera unit.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A base assembly includes a first horizontal brace, a second horizontal brace, a first horizontal interconnection interconnecting front ends of the first and second horizontal braces, a second horizontal interconnection interconnecting rear ends of the first and second horizontal braces, and first, second, third and fourth vertical posts each releasably secured to the underside of the worktable and the rear ends of the first and second horizontal braces; a control switch secured to the front ends of the first and second horizontal braces, and the first interconnection; and a detachable worktable including first and second sliding rods, an opening, first and second bifurcations, a housing; a chute; first and second bossed holes, two opposite third bossed holes, two opposite fourth bossed holes, first and second C-shaped clamps, a transverse second threaded hole, and screws.

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.

Abstract: An electronic device includes: a first substrate; a second substrate, disposed opposite to the first substrate; an insulating layer, disposed on a surface of the first substrate away from the second substrate; and a metal layer, disposed on a surface of the second substrate away from the first substrate, wherein a width of the insulating layer is different from a width of the metal layer.

Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.

Abstract: In some examples, a device can include a first antenna having a first wireless connection with a first computing device, a second antenna having a second wireless connection with a second computing device, and a controller to determine a signal strength of the first wireless connection and a signal strength of the second wireless connection, designate, in response to the signal strength of the first wireless connection being greater than a threshold signal strength, the first wireless connection as an active connection and the second wireless connection as a standby connection, and cause the peripheral device to communicate with the first computing device via the active connection of the first antenna while maintaining the second wireless connection to the second computing device via the second antenna, where the second wireless connection remains as the standby connection.

Abstract: A light source device includes a light guide plate, an optical adhesive, and a light source element. The light guide plate includes a light guide substrate and an enhancement layer. The light guide substrate has a light incident surface, a first surface, and a second surface. The first surface is opposite to the second surface, and the light incident surface extends between the first surface and the second surface. The enhancement layer is disposed on the light guide substrate. A thickness of the enhancement layer is from 1 micrometer to 25 micrometers and a first refractive index of the light guide substrate is greater than a second refractive index of the enhancement layer. The optical adhesive is interposed between the first surface of the light guide substrate and the optical adhesive. The light source element is disposed beside the light incident surface to emit light toward the light incident surface.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

Abstract: An electronic device is provided, including a main body and a camera module. The camera module has a frame, a lens unit disposed in the frame, a guiding member, and a hinge. The guiding member is affixed to the main body and has a rail and a spring sheet. The hinge pivotally connects to the frame and the guiding member. When the camera module is in the retracted position, the camera module is hidden in a recess of the main body. When the camera module slides out of the recess from the retracted position along the rail into the operational position, the spring sheet is pressed by the hinge to increase the friction between the hinge and the guiding member.

Abstract: A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.

Abstract: A probe cover for an ear thermometer and a grouping method of the same are provided. The probe cover for the ear thermometer includes a conical main body having a closed end and an open end, an annular elastomer, and a flange. The closed end is penetrable by infrared rays, and has different infrared transmittances according to thickness variations of the closed end. The annular elastomer is located between the conical main body and the flange. The flange has a plurality of detection positions, each of which having a positive detection pattern or a negative detection pattern, such that the detection positions are arranged to form a plurality of different detection combinations. The different detection combinations respectively correspond to the different infrared transmittances, and any two of the different detection combinations have the two corresponding infrared transmittances that are different from one another.

Abstract: An active stylus and a method performed by the active stylus are provided. The active stylus includes a touch sensor inside. The touch sensor is arranged corresponding to a preset pen-holding region on an outer surface. The touch sensor is insulated from the pen body, when an external operating subject touches the preset pen-holding region and touches a touch panel, an uplink signal transmitted by the touch panel is coupled to the pen body via the external operating subject, as an uplink interference signal. The signal processing unit is for: generating a compensation signal; obtaining a compensated interference signal generated based on the compensation signal and the uplink interference signal; generating an uplink signal to be processed based on the received uplink signal and the compensated interference signal; and obtaining uplink information based on the uplink signal to be processed.

Abstract: An information handling system may include one or more information handling resources, a main battery configured to power the one or more information handling resources, a heater thermally coupled to the main battery, a supportive battery configured to power the heater, and a control unit communicatively coupled to the supportive battery and configured to control the supportive battery and the heater to heat the main battery.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.