Abstract: A camera module suited for assembled in a casing is provided. The camera module includes a camera and a switch cover. The camera is disposed in the casing and aligned with a camera hole of the casing. The switch cover is slidably disposed in the casing, wherein the switch cover includes a sliding member and a shielding member secured to the sliding member, and a thickness of the shielding member is less than a thickness of the sliding member. The camera hole is seated on a sliding path of the shielding member. The shielding member is suited for blocking between the camera and the camera hole or moving out between the camera and the camera hole. An electronic device is also provided.

Abstract: Disclosed is a stress-resistant trace structure and a piezoelectric detection device made thereof. The stress-resistant trace structure includes a patterned trace layer and a porous anti-stress layer. The patterned trace layer has a non-linear pattern and is configured on the porous anti-stress layer. Specifically, the porous anti-stress layer has a plurality of through holes, and the through holes are vertically interlaced with the non-linear pattern.

Abstract: An apparatus for producing an ingot includes a crucible and a lid. The crucible, as a cylindrical container for accommodating a raw crystal-growing material, has an annular top edge further having an annular non-90° first guiding part. The lid provides a bottom for disposing a seed, and the bottom is furnished thereon a bottom protrusion. An outer wall of the bottom protrusion is furnished with an annular non-90° second guiding part corresponding to the first guiding part. The lid is detachable to cover the crucible by having the bottom protrusion to fit the annular the main inner wall, the first guiding part and the annular second guiding part to contact each other, and a portion of the bottom of the lid surrounding the bottom protrusion to contact the top edge of the crucible.

Abstract: The light emitting diode packaging structure includes a flexible substrate, micro light emitting elements disposed on the flexible substrate, a conductive pad, a redistribution layer, and an electrode pad. The micro light emitting elements have a first surface facing to the flexible substrate and a second surface opposite to the first surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting elements. The redistribution layer covers the micro light emitting elements and the conductive pad. The redistribution layer includes an insulating layer and a circuit layer embedded in the insulating layer. The circuit layer is electrically connected to the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer.

Abstract: A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

Abstract: An antenna structure includes a main ground plane, a protruding ground plane, a feeding radiation element, a connection radiation element, a shorting radiation element, a first radiation element, and a second radiation element. The protruding ground plane is coupled to the main ground plane. The feeding radiation element has a feeding point. The connection radiation element is coupled to the feeding radiation element. The connection radiation element is further coupled through the shorting radiation element to the protruding ground plane. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the connection radiation element. The protruding ground plane further includes an extension portion. The first radiation element is adjacent to the extension portion of the protruding ground plane.

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

Abstract: A planarization process is performed to a wafer. In various embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. A byproduct generated by the planarization process is collected and analyzed. Based on the analysis, one or more process controls are performed for the planarization process. In some embodiments, the process controls include but are not limited to process endpoint detection or halting the planarization process based on detecting an error associated with the planarization process.

Abstract: An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.

Abstract: The present disclosure provides a SARS-CoV-2 vaccine composition and use thereof. The SARS-CoV-2 vaccine composition includes a mutant SARS-CoV-2 spike protein with N-linked glycosylation in N-terminal domain or receptor binding domain, and can effectively elicit an immune response in an individual against different SARS-CoV-2 variants.

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: An antenna module includes an antenna box and a first connection wire. The antenna box can include a first antenna, a second antenna, a first connection terminal, a second connection terminal and a housing. The first and second antennas are located in the housing and the housing has a first opening collectively exposing a portion of the first connection terminal and a portion of the second connection terminal. Each of the first and second antennas is adapted to receive or transmit wireless signals according to one of a plurality of wireless communication standards and the first and second antennas are electrically connected to the first and second connection terminals, respectively. The wireless communication standards can be different from each other.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.

Abstract: The present invention provides a voltage control method for controlling a power supply. The voltage control method comprises the following steps: obtaining a present output voltage value associated with a present gain value; obtaining a predetermined output voltage value associated with a predetermined duty ratio; calculating a target gain value, corresponding to the predetermined duty ratio, according to a gain value formula; performing a weight calculation on the present gain value and the target gain value for generating a buffer gain value; and setting an output voltage command according to the buffer gain value. Wherein the buffer gain value is between the present gain value and the target gain value.

Abstract: A wearable device includes a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, and a fifth radiation element. The first radiation element has a feeding point, and is coupled to a first grounding point on the ground element. A slot region is surrounded by the first radiation element and the ground element. The second radiation element is coupled to a second grounding point on the ground element. The third radiation element is coupled to the second grounding point. The third radiation element and the second radiation element substantially extend in opposite directions. The fourth radiation element and the fifth radiation element are disposed inside the slot region. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the fifth radiation element.

Abstract: An antenna structure includes a ground element, a first radiation element, a second radiation element, a third radiation element, and a nonconductive support element. The first radiation element is coupled to a first grounding point on the ground element. The second radiation element has a feeding point. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to a second grounding point on the ground element. The third radiation element is adjacent to the second radiation element. The first radiation element, the second radiation element, and the third radiation element are disposed on the nonconductive support element. The second radiation element is at least partially surrounded by the first radiation element. The third radiation element is at least partially surrounded by the second radiation element.

Abstract: An accuracy measurement method of an autonomous mobile vehicle, a calculating device, and an autonomous mobile vehicle are provided. The accuracy measurement method includes a distance calculating step, a regression center calculating step, and an average calculating step. The distance calculating step includes a controlling step, a light beam emitting step, an image capturing step, an image analyzing step, and a converting step. The regression center calculating step is performed after the distance calculating step is repeatedly performed by at least two times. The accuracy measurement method is performed to obtain an X-axis offset in an X-axis direction, a Y-axis offset in a Y-axis direction, and an angle deflection of an autonomous mobile vehicle.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.