Abstract: A method of manufacturing using a double patterning method is provided. The double patterning method uses a first developer and a second developer that are different. For example, the first developer may be a positive tone developer for a positive photoresist while the second developer may be a negative tone developer for the positive photoresist. Photoresists having a photoactive compound are also provided that may be useful in double patterning methods.

Abstract: A photo resist layer includes a first region and a second region. A treatment layer is applied to the photo resist layer.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of forming a first mask layer on the material layer and then patterning the first mask layer. The patterned first mask layer has a pattern therein and a plurality of gaps within the patterns and the gaps expose a portion of the material layer. Further, a second mask layer is formed over the material layer and the second mask layer fills the gaps. An interface layer is formed between the patterned first mask layer and the second mask layer. A portion of the second material layer is removed until the top surface of the interface layer is exposed. The interface layer is removed to expose a portion of the material layer and the material layer is patterned by using the patterned first mask layer and the second mask layer as a mask.

Abstract: An apparatus, system, or method for positioning a wafer on a support of a rotatable chuck may improve the accuracy and precision of various wafer edge cuts and wafer profiling at a variety of stages of wafer manufacturing. The apparatus, system, or and/or method may employ one or more of a wafer position calculator to calculate a desired wafer position and to provide desired wafer position information to a wafer arm controller; and a wafer arm controller in communication with the wafer position calculator to provide instructions to adjust a wafer arm to position the wafer on the support according to the desired wafer position. Various sensor detectors and sensor lights or other mechanisms for sensing the position of a wafer may also be used.

Abstract: A method for patterning a multi-layer film in a semiconductor device is provided. The semiconductor device comprises a substrate and a multi-layer film on the substrate. The multi-layer film comprises N conductive layers and N dielectric layers alternatingly stacked, and 2N contact plugs. The Nth dielectric layer is formed at the top of the multi-layer film. The distances between the centers of each adjacent contact plugs are the same.

Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract: A baking apparatus including a hot plate and a substrate rotation member is provided. The hot plate has a heating surface. The substrate rotation member includes a rotation ring and a plurality of support arms. The rotation ring is configured to surround the hot plate. The support arms are disposed over the heating surface of the hot plate. Each of the support arms includes a connection part and a support part, wherein the connection part is configured to connect the rotation ring and the support part, and a supporting surface of the support part for supporting the substrate is higher than the heating surface of the hot plate.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer. The material layer has a first hard mask layer and a second hard mask layer successively formed thereon. Then, the second hard mask layer is patterned to form a plurality of openings therein. A patterned photoresist layer is formed to cover the second hard mask layer and the patterned photoresist layer exposes a portion of the openings. The first hard mask layer with the patterned photoresist layer and the patterned second hard mask layer together as a mask. Then, the patterned photoresist layer and the patterned second hard mask layer are removed. The material layer is patterned with the patterned first hard mask layer as a mask.

Abstract: An apparatus for wafer edge exposure comprises a first exposure unit and a second exposure unit. The first exposure unit includes a first light source to emit first light of multiple wavelengths, and a first mask to direct the first light toward a first area at an edge portion of a wafer. The second exposure unit includes a second light source to emit second light of a single wavelength, and a second mask to direct the second light toward a second area at the edge portion of the wafer. The second area encloses a transition area that borders the first area under the first mask.

Abstract: The invention is directed to an overlay mark in a first material layer in an overlay alignment region of a wafer and the first material layer is made from a first material. The overlay mark includes a plurality of mark regions and each of the mark regions comprises a plurality mark elements embedded in the first material layer. Each of the mark elements is made of a second material different from the first material of the first material layer and the mark elements evenly distribute in the mark region.

Abstract: A method of manufacturing a memory device is disclosed. The method includes providing a substrate, forming a number of memory sectors on the substrate, wherein each of the memory sectors is coupled to an adjacent one via a first diffused region in the substrate and is coupled to another adjacent one via at least one second diffused region in the substrate, forming a first dielectric layer on the memory sectors, forming a first conductive structure through the first dielectric layer to the first diffused region, and at least one second conductive structure through the first dielectric layer to the at least one second diffused region, forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure, and etching back the first conductive structure.

Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.

Abstract: An overlay mark is described, including N sets of parallel x-directional linear patterns respectively defined by N (?2) exposure steps and N sets of parallel y-directional linear patterns respectively defined by the N exposure steps, and a set of parallel x-directional photoresist bars and a set of parallel y-directional photoresist bars both formed in a lithography process. The N sets of x-directional linear patterns and the set of x-directional photoresist bars are arranged in parallel. The N sets of y-directional linear patterns and the set of y-directional photoresist bars are arranged in parallel.

Abstract: A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark.

Abstract: An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape.

Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.

Abstract: A method of patterning a target layer on a substrate is described. A patterned photoresist layer is formed over the target layer, wherein the patterned photoresist layer has unexposed parts as separate islands and each unexposed part has a low proton concentration at least in its sidewalls. Acid-crosslinked polymer layers are formed only on the sidewalls of each unexposed part. A flood exposure step is performed to the substrate. A baking step is performed to the patterned photoresist layer. A development step is performed to remove the previously unexposed parts. The target layer is etched with the acid-crosslinked polymer layers as a mask.

Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.

Abstract: An integrated circuit that includes a line end created through use of a mask that controls line end shortening and corner rounding arising from proximity effects is provided. The mask includes a main feature having opaque and transmissive areas arranged to reflect a patterned feature of the line end, at least one of an opaque edge or a transmissive edge located at each end of the main feature, wherein the opaque edge has a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge has a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature.