Abstract: The present disclosure, in some embodiments, relates to an integrated antenna structure. The structure includes an excitable element and a first ground plane. The first ground plane is disposed between a first surface of a semiconductor substrate and the excitable element. A first line that is normal to the first surface of the semiconductor substrate extends through both the first ground plane and the excitable element. A second ground plane is separated from the first ground plane by the semiconductor substrate. The second ground plane is electrically coupled to the first ground plane.

Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.

Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.

Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.

Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.

Abstract: A method (of generating a layout diagram) includes: generating a cell (which represents a circuit) including first and second side boundaries which are substantially parallel and extend in a first direction, a first wiring pattern which is an intra-cell wiring pattern that extends in a second direction (substantially perpendicular to the first direction) and represents a conductor of a first signal which is internal to the circuit, and a second wiring pattern which extends in the first direction and represents a conductor of a second signal of the circuit; configuring the intra-cell wiring pattern so that a first end is located substantially a minimum boundary offset interior to the first side boundary; and configuring the second wiring pattern so that a portion thereof has a first end which extends exterior to the first side boundary by a protrusion length which is substantially greater than the minimum boundary offset.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: The present disclosure describes a semiconductor structure includes a first chip with a first conductive line and a first conductive island formed on the first conductive line. The first chip also includes a first plurality of vias formed in the first conductive island and electrically coupled to the first conductive line. The semiconductor structure further includes a second chip bonded to the first chip, where the second chip includes a second conductive line and a second conductive island formed on the second conductive line. The second chip also includes a second plurality of vias formed in the second conductive island and electrically coupled to the second conductive line.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.