Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.

Abstract: A method and a system for detecting an application program version with abnormal power consumption are provided. The method includes the following. A power consumption database of multiple versions of a target application is established. Power consumption information of a target version of the target application is obtained. According to the power consumption database and the power consumption information, whether the target version of the target application has a first abnormal power consumption state evaluated based on different versions of the target application is determined. In response to the first abnormal power consumption state, an abnormal power consumption prompt corresponding to the target version is generated.

Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.

Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.

Abstract: The present application provides a gesture determining method and an electronic device. The gesture determining method includes: sensing a control gesture through at least one motion sensor, and correspondingly generating sensing data; sequentially segmenting the sensing data into a plurality of streaming windows according to a unit of time, each streaming window including a group of sensing values; determining whether a sensing value in a streaming window is greater than a critical value, and triggering subsequent gesture recognition when the sensing value is greater than the critical value; and performing a recognition operation on the streaming window by using a gesture recognition model to consecutively output a recognition result; and determining whether the recognition result meets an output condition, and outputting a predicted gesture corresponding to the recognition result when the recognition result meets the output condition.

Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.

Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.

Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.

Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.

Abstract: A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N?3, Ma?2, Ma+Mb?N?1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ?R, and 0<|?R|?10%.

Abstract: A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N?3, Ma?2, Ma+Mb?N?1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ?R, and 0<|?R|?10%.

Abstract: A nail polish composition system includes (a) a base coat nail polish composition including organic solvents, film-forming compounds, plasticizers, and one or more additives; and (b) a top coat nail polish composition including a mixture of cyanoacrylates and a methacrylate. The base coat nail polish composition is applied to a fingernail to form a base coat film. Thereafter, the top coat nail polish composition is applied on or over the base coat film to form a top coat film. The nail polish composition system can significantly shorten the time required for drying the base and top coat nail polish compositions. In addition, the nail polish composition system may be applied without dipping the fingernail in powder glaze.

Abstract: A nail glue composition contains Beta-methoxyethyl cyanoacrylate, octyl cyanoacrylate, and polymethyl methacrylate. The nail glue composition is substantially odorless and has increased softness.

Abstract: A nail glue composition contains Beta-methoxyethyl cyanoacrylate, octyl cyanoacrylate, and polymethyl methacrylate. The nail glue composition is substantially odorless and has increased softness.

Abstract: The present invention relates to a lamp for use in curing gel polish applied to nails, such as fingernails or toenails. The lamp includes a housing having an opening for receiving, at least, a part of a hand including one or more fingers or a part of a foot including one or more toes. The lamp also includes one or more retractable feet attached to a bottom of the housing adjacent a front end thereof for elevating the front end of the housing so as to facilitate the insertion or removal, or the proper positioning, of the part of the foot or the hand in or from the opening of the housing. The lamp also includes a bottom plate and a mechanically releasable mechanism for removably attaching the bottom plate to the bottom of the housing.

Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.