Abstract: A signal generating apparatus, applicable in a universal serial bus (USB) device, includes: a first determining circuit for receiving a data signal to determine if the data signal is generated by the universal serial bus device, and generating a first determined result; a second determining circuit coupled to the first determining circuit for receiving the data signal and the first determined result to determine a transmitting mode corresponding to the data signal according to the first determined result, and generating a second determined result; and a frequency generating circuit coupled to the second determining circuit for generating a first clock signal utilized for synchronizing the data signal according to the second determined result.

Abstract: A clock generating circuit includes: a phase detector for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a controllable oscillator for generating a plurality of output clocks according to the control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; a feedback circuit for generating the input clock according to the feedback clock; and a phase difference comparator for comparing the plurality of phases corresponding to the plurality of output clocks respectively with a data phase of a data signal to generate a compared result, and generating the phase select signal according to the compared result.

Abstract: A clock generating circuit includes: a phase detector for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a controllable oscillator for generating a plurality of output clocks according to the control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; a feedback circuit for generating the input clock according to the feedback clock; and a phase difference comparator for comparing the plurality of phases corresponding to the plurality of output clocks respectively with a data phase of a data signal to generate a compared result, and generating the phase select signal according to the compared result.

Abstract: A clock generating circuit includes: a phase detector for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a filter for filtering the control signal to generate a filtered control signal; a controllable oscillator for generating a plurality of output clocks according to the filtered control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; and a feedback circuit for generating the input clock according to the feedback clock.

Abstract: A clock generating circuit includes: a phase detector for detecting a phase difference between an input clock and a reference clock to generate a control signal corresponding to the phase difference; a filter for filtering the control signal to generate a filtered control signal; a controllable oscillator for generating a plurality of output clocks according to the filtered control signal, wherein the plurality of output clocks correspond to an oscillating frequency and correspond to a plurality of different phases respectively; a phase selector for selecting an output clock as a feedback clock from the plurality of output clocks according to a phase select signal; and a feedback circuit for generating the input clock according to the feedback clock.

Abstract: A signal generating apparatus, applicable in a universal serial bus (USB) device, includes: a first determining circuit for receiving a data signal to determine if the data signal is generated by the universal serial bus device, and generating a first determined result; a second determining circuit coupled to the first determining circuit for receiving the data signal and the first determined result to determine a transmitting mode corresponding to the data signal according to the first determined result, and generating a second determined result; and a frequency generating circuit coupled to the second determining circuit for generating a first clock signal utilized for synchronizing the data signal according to the second determined result.

Abstract: A penicillin G biosensor, systems comprising the same, and measurement using the systems. The penicillin G biosensor has an extended gate field effect transistor (EGFET) structure and comprises a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, a sensing unit comprising a substrate, a tin oxide film on the substrate, and a penicillin G acylase film immobilized on the tin oxide film, and a conductive wire connecting the MOSFET and the sensing unit.

Abstract: A penicillin G biosensor, systems comprising the same, and measurement using the systems. The penicillin G biosensor has an extended gate field effect transistor (EGFET) structure and comprises a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, a sensing unit comprising a substrate, a tin oxide film on the substrate, and a penicillin G acylase film immobilized on the tin oxide film, and a conductive wire connecting the MOSFET and the sensing unit.

Abstract: An apparatus for ring-back constriction is provided. The apparatus includes a comparator, a termination controller, a termination variable resistor, a constriction controller, and a constriction variable resistor. The comparator is coupled to the transmission line, for comparing the line signal with a reference voltage, and accordingly outputting a comparison signal. The termination controller is coupled to the comparator, for outputting a termination control signal to adjust the resistance of the termination variable resistor. The constriction controller is coupled to the comparator for outputting a constriction signal to adjust the resistance of the constriction variable resistor. The ring-back effect is constricted due to impedance matchtermination voltage when an undershot occurs.

Abstract: A penicillin G biosensor, systems comprising the same, and measurement using the systems. The penicillin G biosensor has an extended gate field effect transistor (EGFET) structure and comprises a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, a sensing unit comprising a substrate, a tin oxide film on the substrate, and a penicillin G acylase film immobilized on the tin oxide film, and a conductive wire connecting the MOSFET and the sensing unit.

Abstract: A charge pump and a voltage doubler are provided. The charge pump minimizes the difference in voltage between the terminals of a MOS transistor by serially connecting PMOS and NMOS transistors inside the charge pump circuit. The charge pump is able to provide a higher voltage while avoiding a large voltage difference at the gate-source, gate-base and gate-drain interfaces.

Abstract: A output buffer circuit comprises a pull-up transistor, a boost transistor and a boost-controlling circuit. The pull-up transistor has a drain connected to a voltage source, a source connected to an I/O node and a gate connected to a data out through a voltage-boosting node. The boost transistor has a drain connected to the voltage source, and a source connected to the voltage-boosting node. The boost-controlling circuit has an input connected to the I/O node and an output connected to a gate of the boost transistor. The input of the boost-controlling circuit senses an excessive voltage at the I/O node and the output thereof turns on the boost transistor. Therefore, a gate voltage of the pull-up transistor is sustained to a predetermined high level when the pull-up transistor is turned off, and a voltage difference between the gate voltage and a source voltage of the pull-up transistor is reduced.

Abstract: A charge pump and a voltage doubler are provided. The charge pump minimizes the difference in voltage between the terminals of a MOS transistor by serially connecting PMOS and NMOS transistors inside the charge pump circuit. The charge pump is able to provide a higher voltage while avoiding a large voltage difference at the gate-source, gate-base and gate-drain interfaces.

Abstract: A self-compensation circuit for terminal resistors includes a current mirror, a reference resistor, a comparator and a plurality of terminal resistors. The current mirror provides a first current through the reference resistor to form a first voltage and a second current through an external resistor to form a second voltage. The comparator compares the first voltage and the second voltage and generates an output voltage that is able to be feedback to the control terminal of the reference resistor. The control terminal of each terminal resistor is connected to the output end of the comparator, thus the resistance of each terminal resistor is able to be proportional to the resistance of the external resistor.

Abstract: A output buffer circuit comprises a pull-up transistor, a boost transistor and a boost-controlling circuit. The pull-up transistor has a drain connected to a voltage source, a source connected to an I/O node and a gate connected to a data out through a voltage-boosting node. The boost transistor has a drain connected to the voltage source, and a source connected to the voltage-boosting node. The boost-controlling circuit has an input connected to the I/O node and an output connected to a gate of the boost transistor. The input of the boost-controlling circuit senses an excessive voltage at the I/O node and the output thereof turns on the boost transistor. Therefore, a gate voltage of the pull-up transistor is sustained to a predetermined high level when the pull-up transistor is turned off, and a voltage difference between the gate voltage and a source voltage of the pull-up transistor is reduced.

Abstract: An apparatus for ring-back constriction is provided. The apparatus includes a comparator, a termination controller, a termination variable resistor, a constriction controller, and a constriction variable resistor. The comparator is coupled to the transmission line, for comparing the line signal with a reference voltage, and accordingly outputting a comparison signal. The termination controller is coupled to the comparator, for outputting a termination control signal to adjust the resistance of the termination variable resistor. The constriction controller is coupled to the comparator for outputting a constriction signal to adjust the resistance of the constriction variable resistor. The ring-back effect is constricted due to impedance matchtermination voltage when an undershot occurs.