Patents by Inventor Chin Hung

Chin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176191
    Abstract: An electronic device includes a first substrate, a first protrusion, a second protrusion and a plurality of third protrusions. The first substrate includes an edge, a first region, and a second region. The first substrate includes a surface. The first protrusion is in the first region. A maximum distance from the surface to a top surface of the first protrusion is defined as a first distance. The second protrusion is in the second region. A maximum distance from the surface to a top surface of the second protrusion is defined as a second distance. The first protrusion is disposed between two of the third protrusions. A maximum distance from the surface to a top surface of the third protrusion is defined as a third distance. The first distance is different from the second distance, and the third distance is less than the first distance.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 30, 2024
    Inventors: Tang-Chin HUNG, Zhi-Fu HUANG
  • Publication number: 20240170954
    Abstract: A motor control method for coupled an electronic vehicle is provided. The motor controller controls a motor and is powered by a battery. The motor control method includes: when a main relay of the motor controller suddenly breaks contact, in a first phase, feeding back a surge current into the battery to suppress the surge current by a diode and a first current limit resistor of a first protecting circuit of the motor controller; and, in a second phase, conducting a discharge switch of a second protecting circuit of the motor controller by a control unit of the motor controller, and releasing the surge current to a reference voltage range by the discharge switch and a second current limit resistor of the second protecting circuit.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 23, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Nan-Hsiung TSENG, Bing-Ren CHEN, Shin-Hung CHANG, Chin-Hone LIN
  • Patent number: 11990507
    Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 11987566
    Abstract: The present invention provides a novel compound for effectively preventing nerve damage and protecting nerves, and a preparation method thereof. Besides, the present invention also provides a pharmaceutical composition comprising the novel compound, and a use of the novel compound for preventing nerve damage and protecting nerves.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: May 21, 2024
    Assignee: GENHEALTH PHARMA CO., LTD.
    Inventors: Lain-Tze Lee, Hui-Ping Tsai, Yi-Wen Lin, Shu-Fen Huang, Shih-Hung Liu, Chin-Wei Liu, Pi-Tsan Huang, Mei-Hui Chen
  • Publication number: 20240161672
    Abstract: An electronic circuit including a plurality of common terminals, a first circuit, a second circuit, and a plurality of switch units is provided. The first circuit is configured to output display driving signals to data lines of a display panel via the common terminals. The second circuit is configured to receive fingerprint sensing signals from fingerprint sensing lines of the display panel via the common terminals. Each of the switch units includes a first terminal coupled to one of the common terminals and a plurality of second terminals coupled to the first circuit and the second circuit. The switch units are grouped into a plurality of groups, and each group corresponds to a fingerprint sensing channel of the second circuit.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Huan-Teng Cheng, Ting-Hsuan Hung, Tzu-Wen Hsieh, Wei-Lun Shih, Huang-Chin Tang
  • Publication number: 20240159105
    Abstract: A motorized blind and a manual switching clutch structure thereof are disclosed. The motorized blind includes a blind assembly, a spring power module, an electric motor module and the manual switching clutch structure. The blind assembly includes a bottom rail which can be driven by the spring power module to move. The manual switching clutch structure is disposed between the spring power module and the electric motor module. By rotating a knob of the manual switching clutch structure, the motorized blind can be switched between a motor driving mode in which the electric motor module participates in the movement of the bottom rail by driving the spring power module, and a manual driving mode in which the spring power module individually participates in the movement of the bottom rail.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 16, 2024
    Applicant: Nien Made Enterprise Co., Ltd.
    Inventors: Chao-Hung Nien, Chin-Chu Chiu, Hui-Ping Cheng
  • Patent number: 11983475
    Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
  • Patent number: 11984419
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 11979156
    Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: May 7, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen
  • Publication number: 20240147556
    Abstract: In some examples, a device can include a first antenna having a first wireless connection with a first computing device, a second antenna having a second wireless connection with a second computing device, and a controller to determine a signal strength of the first wireless connection and a signal strength of the second wireless connection, designate, in response to the signal strength of the first wireless connection being greater than a threshold signal strength, the first wireless connection as an active connection and the second wireless connection as a standby connection, and cause the peripheral device to communicate with the first computing device via the active connection of the first antenna while maintaining the second wireless connection to the second computing device via the second antenna, where the second wireless connection remains as the standby connection.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Min-Hsu Chuang, Xin-Chang Chen, Pai-Cheng Huang, Chin-Hung Ma, Shih-Yen Cheng
  • Patent number: 11966107
    Abstract: An anti-peep display device includes a display module and an anti-peep module disposed on the display module. The anti-peep module includes the following features. The first light incident surface faces the display surface, the second and third light incident surfaces are located on opposite sides of the first light incident surface, the first condensing portion is disposed corresponding to the second light incident surface and the first light source, the second condensing portion is disposed corresponding to the third light incident surface and the second light source, the first and second condensing portions convert beams of the first and second light sources into anti-peep beams with a beam angle less than 10 degrees, and the optical microstructures reflect the anti-peep beams and exit the anti-peep beams from the light guide plate. The present invention also provides an anti-peep method applicable to the anti-peep display device.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: April 23, 2024
    Assignee: CHAMP VISION DISPLAY INC.
    Inventors: Chung-Hao Wu, Hsin-Hung Lee, Chin-Ku Liu, Chun-Chien Liao, Wei-Jhe Chien
  • Publication number: 20240128127
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-l Fu, Chun-ya Chiu, Chi-Ting Wu, Chin-HUNG Chen, Yu-Hsiang Lin
  • Publication number: 20240128414
    Abstract: A light-emitting device is provided. The light-emitting device includes a light-emitting unit and a light-conversion structure disposed on the light-emitting unit, wherein the light-conversion structure includes a quantum dot layer and an etching blocking layer disposed on one of the surfaces of the quantum dot layer.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 18, 2024
    Inventors: Shiou-Yi KUO, Chin-Hung LUNG, Yu-Chun LEE, Hung-Chun TONG
  • Patent number: 11960769
    Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 16, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen
  • Publication number: 20240118806
    Abstract: Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.
    Type: Application
    Filed: October 6, 2022
    Publication date: April 11, 2024
    Applicant: Macronix International Co., Ltd.
    Inventors: Chin-Hung Chang, Ken-Hui Chen, Chun-Hsiung Hung
  • Publication number: 20240120157
    Abstract: A keyswitch structure includes a baseplate, a keycap disposed over the baseplate and configured to be movable relative to the baseplate, a membrane switch disposed between the keycap and the baseplate and configured to have one or more buffer portions with two open edges opposite to each other, and a first linking bar connected to the keycap and disposed between the keycap and the membrane switch. The first linking bar has a first long side and a first short side connected to each other. When the keycap moves relative to the baseplate, the one or more buffer portions provide buffer to the first short side and/or an end section of the first long side.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 11, 2024
    Inventors: YU-MING HUANG, CHIN-HUNG LIN
  • Publication number: 20240110829
    Abstract: A display device and a light detection module are provided. The display device includes a display panel and the light detection module. The light detection module is capable of detecting an optical feature of a display surface of the display panel, and includes a shaft portion, a rod portion, and a light detector. The shaft portion has a shaft extension direction. The rod portion has a rod extension direction, and takes the shaft portion as a rotation shaft. An included angle between the rod extension direction and the shaft extension direction is between 125 degrees and 145 degrees.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 4, 2024
    Applicant: CHAMP VISION DISPLAY INC.
    Inventors: Chin-Ku Liu, Chia-Hung Yu
  • Publication number: 20240098652
    Abstract: In an example, a computing device may include a first radio device including a first antenna, a second radio device including a second antenna, and a basic input/output system (BIOS). The BIOS may establish a communication with the first and second radio devices. Further, the BIOS may receive first transmission status information associated with the first antenna from the first radio device and second transmission status information associated with the second antenna from the second radio device. Furthermore, the BIOS may detect a condition indicative of a combined transmit power of the first and second antennas exceeding a radio frequency exposure threshold based on the first and second transmission status information. The BIOS may instruct the first radio device, the second radio device, or both to perform a mitigation action to maintain the combined transmit power at or below the radio frequency exposure threshold.
    Type: Application
    Filed: February 23, 2021
    Publication date: March 21, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chih-Hung Chien, Chien-pai Lai, Chin-Hung Ma
  • Publication number: 20240097323
    Abstract: In some examples, a device can include an antenna to emit waves in a radiation pattern having a first beamwidth, a directional radiation control device located in a path of the waves, where the directional radiation control device is to receive the waves from the antenna and is shaped to cause the waves to be directed in a different radiation pattern having a second beamwidth that is larger than the first beamwidth.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Chin-Hung Ma, Pai-Cheng Huang, Po Chao Chen, Shih-Huang Wu
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su