Patents by Inventor Chin-Hung Chen

Chin-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295160
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Application
    Filed: April 9, 2019
    Publication date: September 17, 2020
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 10755919
    Abstract: A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20200203231
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200144100
    Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20200144099
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10607882
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10529825
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190313906
    Abstract: A one-touch data transmission module includes a data receiving unit, for receiving a transmission datum sent by a physiological data analyzer; a control unit, electrically connected to the data receiving unit, for obtaining the transmission datum received by the data receiving unit; a memory unit, electrically connected to the control unit, for storing the transmission datum; a communication unit, electrically connected to the control unit, for sending the transmission datum to a designated place; a power unit, for supplying power to the data receiving unit, the memory unit and the communication unit; a trigger button, electrically connected to the control unit, for triggering the control unit to start the data receiving unit to receive the transmission datum, the received transmission datum being send by the communication unit. The data transmission module provides the functions of simple operation and real-time data transmission for an elderly person.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 17, 2019
    Inventors: Jin-Ping Chen, Chin-Hung Chen
  • Publication number: 20190296124
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.
    Type: Application
    Filed: April 11, 2018
    Publication date: September 26, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10395991
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190221469
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10347526
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate structure, and a conductive element. The gate structure is on the substrate. The gate structure includes a gate electrode and a cap layer on the gate electrode. The conductive element is adjoined with an outer surface of the gate structure. The conductive element includes a lower conductive portion and an upper conductive portion electrically connected on the lower conductive portion and adjoined with the cap layer. The lower conductive portion and the upper conductive portion have an interface therebetween. The interface is below an upper surface of the cap layer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20190206672
    Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.
    Type: Application
    Filed: February 11, 2019
    Publication date: July 4, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190172752
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10249488
    Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190076911
    Abstract: In one aspect, a method for forging a vehicle wheel with three-dimensional features may include steps of utilizing toe-clamps and center collets to reduce chatter marks and the effects of vibrations and harmonics; employing a parametric CNC program which allows for feed rates and spindle RPM speeds that are specific to the process of the vehicle wheel design; utilizing end-mills, bull-nose end-mills, ball-mills, chamfer tools, V-tools, custom rivet tools, and other commonly used CNC milling tools to machine the sides of the spokes on the wheels; utilizing a coolant to operate the CNC machine; providing a tool to make the three-dimensional features on the wheel; cleaning the wheel to remove coolant and debris remaining on the wheel; and painting selected areas of the wheel.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 14, 2019
    Inventor: Chin Hung Chen
  • Patent number: 10171265
    Abstract: A method for sending data includes receiving, at a first station of a plurality of stations, a trigger frame from an access point of a wireless network. The method also includes determining a downlink channel estimation based on the trigger frame and sending the downlink channel estimation to the access point. The method further includes receiving uplink channel data from the access point in response to sending the downlink channel estimation. The method also includes sending data to the access point based on the uplink channel data.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: January 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Hung Chen, Ning Zhang, Youhan Kim
  • Patent number: D849639
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: May 28, 2019
    Inventor: Chin Hung Chen
  • Patent number: D864835
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 29, 2019
    Inventor: Chin Hung Chen
  • Patent number: D875639
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: February 18, 2020
    Inventor: Chin Hung Chen