Abstract: A memory-testing device for testing a memory is provided. The memory-testing device includes a testing circuitry and a register. The testing circuitry is coupled to the memory for testing performance of the memory. The register is coupled to the testing circuitry and inputted by a testing clock signal, wherein the testing clock signal is different from an original clock signal of the memory and/or the testing circuitry. The testing clock signal is utilized for adjusting the time when the memory-testing device latches data from the memory to decrease a timing slack of the memory-testing device.

Abstract: A memory-testing device for testing a memory is provided. The memory-testing device includes a testing circuitry and a register. The testing circuitry is coupled to the memory for testing performance of the memory. The register is coupled to the testing circuitry and inputted by a testing clock signal, wherein the testing clock signal is different from an original clock signal of the memory and/or the testing circuitry. The testing clock signal is utilized for adjusting the time when the memory-testing device latches data from the memory to decrease a timing slack of the memory-testing device.

Abstract: A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters.

Abstract: A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters.

Abstract: An error correction method for a memory device is disclosed. A base reading of a memory device is performed, and an error correction code (ECC) decoding is performed on the data read out of the memory device. The memory device is further read when the result of the ECC decoding is not strongly determined, wherein extra information acquired in the further reading of the memory device is used in the ECC decoding.

Abstract: The invention discloses a message playback apparatus. The message playback apparatus includes a receiving module, an analysis module, a storage module, and an output module. The receiving module is used for receiving a plurality of external messages. The analysis module is used for selecting at least one target message from the external messages. The storage module is used for storing the at least one target message. The output module is used for reading out the at least one target message and transforming the at least one target message to an output signal.

Abstract: The invention discloses a simulating apparatus of facial expression comprising a casing and a facial expression module, wherein the casing has a transparent surface, and the facial expression module is configured in the casing and behind the transparent surface. The facial expression module comprises a plurality of light guiding components, a plurality of light sources, and a control module. The lighting guiding devices is used for making up a plurality of facial patterns; the light sources are configured at one side of the light guiding components, and the light, emitted by the light sources, can be transmitted through the light guiding components to bring the facial patterns a lighting effect; the control module is electrically connected to the light sources for selectively controlling the light sources to emit light.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.